대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 ITC-CSCC -2
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- Pages.1188-1191
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- 2002
CMOS Synaptic Model Considering Spatio-Temporal Summation of lnputs
- Fujita, Takeshi (Graduate School of Science & Technology, Nihon University) ;
- Matsuoka, Jun (Graduate School of Science & Technology, Nihon University, Presently with Toyo Communication Equipment Co., Ltd.) ;
- Saeki, Katsutoshi (College of Science & Technology, Nihon University) ;
- Sekine, Yoshifumi (College of Science & Technology, Nihon University)
- 발행 : 2002.07.01
초록
A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.
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