Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06d
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- Pages.235-238
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- 2002
DCT Implementation on FPGA for HDTV Encoder
FPGA를 이용한 HDTV인코더를 위한 DCT회로의 구현
Abstract
This paper presents a way of a novel FPGA implementation of DCT. It shows how to limit the required bits on each DCT processing step, instead of implementing high-cost 64-bit floating-point arithmetic of IEEE Std 754-1985 on FPGA. ID-DCT implementation has been done which operates at 30 frame per second with 1920
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