Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.06b
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- Pages.325-328
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- 2002
32 Bit RISC Core modeling using SystemC
Abstract
In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).
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