Design of JPEG Core for Real-Time Image Compression and Decompression

실시간 영상 압축 및 복원 기능을 갖는 JPEG 코어 설계

This paper describes the design and implementation results of JPEG core, based on the ITU-T Recommendation T.81. We designed the RTL circuit in Verilog HDL, making reference to the JPEG program from the Independent JPEG Group. The circuit has been simulated with Verilog-XL, synthesized with Design Compiler and verified using Altera FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in image processing SOC.