Improvement of Boron Penetration and Reverse Short Channel Effect in 130nm W/WNx/Poly-Si Dual Gate PMOSEET for High Performance Embedded DRAM

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.