대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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- Pages.347-350
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- 2002
WRR 알고리즘 지원 시스톨릭 구조 가상 출력 큐
Systolic Architecture Vitrual Output Queue with Weighted Round Robin Algorithm
초록
In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.
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