8-bit 60Ms/s 파이프라인 아날로그 디지털 변환기

A Pipelined 60Ms/s 8-bit Analog to Digital Converter

  • 조은상 (성균관대학교 전기전자 및 컴퓨터공학과) ;
  • 정강민 (성균관대학교 전기전자 및 컴퓨터공학과)
  • 발행 : 2001.06.01

초록

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

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