Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.11b
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- Pages.353-356
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- 2000
IEEE-754 Floating-Point Divider for Embedded Processors
내장형 프로세서를 위한 IEEE-754 고성능 부동소수점 나눗셈기의 설계
Abstract
In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors and supports all rounding modes defined by IEEE 754 standard, is designed using the series expansion algorithm. This divider shares and fully utilizes the two MAC units for quadratical convergence to the correct quotient. The area increase of two MAC units due to the division is minimized in this design, so that it can be suitable for embedded processors. The tested HDL codes are synthesized and optimized with 0.35
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