대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
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- Pages.85-88
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- 2000
Leading 0/1 검출 기능을 부가한 곱셈기
A Multiplier with Leading 0/1 Detector
초록
This paper describes the design of multiplier that receives two N-bit number and produces an N-bit product, with leading 0/l detector logic for an overflow prediction. A leading 0/l detector for two's input predict a scope of output. The part of partial products sum of N most-significant bits is exchanged for an overflow prediction. Therefore this multiplier requires less gates for the implementation about 45% than general multipliers.
키워드