대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 ITC-CSCC -1
- /
- Pages.399-402
- /
- 2000
A Scheduling Approach with Component Selection
- Harashima, Katsumi (Faculty of Engineering, Osaka Institute of Technology) ;
- Satoh, Hisashi (Faculty of Engineering, Osaka Institute of Technology) ;
- Hiro, Daisuke (Faculty of Engineering, Osaka Institute of Technology) ;
- Kutsuwa, Toshiro (Faculty of Engineering, Osaka Institute of Technology)
- 발행 : 2000.07.01
초록
The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.
키워드