Study of one chip SEED block cipher

SEED 블록 암호 알고리즘의 단일 칩 연구

  • 신종호 (한국외국어대학교 전자제어공학과) ;
  • 강준우 (한국외국어대학교 전자제어공학과)
  • Published : 2000.06.01

Abstract

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

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