대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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- Pages.145-148
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- 2000
마이크로파이프라인 구조의 16bit 비동기 곱셈기
Asynchronous 16bit Multiplier with micropipelined structure
초록
A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65
키워드