그레이 레벨 연결성 복원 하드웨어 구조

A Hardware Architecture for Retaining the Connectivity in Gray - Scale Image

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents disconnecting in the gray-scale image thinning To perform the image thinning in a real time which find a skeleton in image, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture is consists of three blocks, PS(Parallel to Serial) Converter and State Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examine the connectivity of the central pixel by searching the data from the PS Converter. the 3$\times$3 gray level image determines. The Ridge Checker determines whether the central pixel is on the skeleton or not The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.