대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1999년도 하계종합학술대회 논문집
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- Pages.353-356
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- 1999
자체귀환형 2단 고리발진기를 이용한 고속 CMOS PLL 설계
Design of a High Speed CMOS PLL with a Two-stage Self-feedback Ring Oscillator
초록
A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6
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