Implementation of Arithmetic Processor Using Multi-Valued Logic

다치 논리를 이용한 연산기 구현

  • 양대영 (동의대학교 전자공학과) ;
  • 김휘진 (동의대학교 전자공학과) ;
  • 박진우 (동의대학교 전자공학과) ;
  • 송홍복 (동의대학교 전자공학과)
  • Published : 1998.05.01

Abstract

This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

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