대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1998년도 추계종합학술대회 논문집
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- Pages.1157-1160
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- 1998
2차원 DWT/IDWT의 블록 데이터 플로우 구조 설계
Design of a Block Data Flow Architecture for 2-D DWT/IDWT
초록
This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256
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