BIST Architecture for Datapath Megacells

데이터 패스 메가셀을 위한 BIST 구조

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.