Design Error Searching Algorithm in VHDL Behavioral-level using Hierarchy

계층성을 이용한 VHDL 행위 수준에서의 설계 오류 탐색 알고리듬

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.