Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Static Latched DCVSL Circuits for Asynchronous Pipeline Scheme

비동기 파이프라인 구조를 위한 정적 래치 DCVSL 회로

  • 김영우 (고려대학교 전자공학과 ASIC 설계 기술 연구실) ;
  • 김수원 (고려대학교 전자공학과 ASIC 설계 기술 연구실)
  • Published : 1998.10.01
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Abstract

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

Keywords