조합회로에 대한 게이트 지연 검사 패턴 생성기의 속도 향상에 관한 연구

A Study on Speed Improvement of Gate Delay Test Generator for Combinational Circuits

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.