Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1998.10a
- /
- Pages.199-202
- /
- 1998
Selective FEC using Multi-Stage Viterbi Coder
다단 Viterbi 부호기를 사용한 가변 에러정정 기법
- Park, Tae-Kuen (Electronics Engineering, Myongji University) ;
- Lee, Jun-Hwa (Electronics Engineering, Myongji University) ;
- Park, Jae-Hyun (Electronics Engineering, Myongji University) ;
- Choi, Byung-Suk (Electronics Engineering, Myongji University) ;
- Park, Hyun-Min (Electronics Engineering, Myongji University)
- Published : 1998.10.01
Abstract
In this paper, to reduce BER(Bit Error Rate) in satellite ATM Networks, a new scheme for FEC(Forward Error Corection) using multi-stage Viterbi coder is proposed. In terms of structural complexity, proposed multi-stage Viterbi coder is simpler than the traditional single-stage coder based on the same BER performances. and, through simulation, proposed coder shows excellent error correction capabilities, compared with traditional FEC schemes. Also, we propose a selective FEC mechanism that adaptively changes the number of stages to satisfy the QoS(Quality of Service) requirements. This Selective scheme can be easily implemented using the PLCP(Physical Layer Convergence Protocol) frame structure.
Keywords