A VLSI Design of Modified Transform RS Decoder

개선된 변환영역 RS 복호기의 VLSI 설계

In this paper, a RS(Reed-Solomon) docoder is designed in the transform domain instead of most time domain. The transform RS decoder have simpler structure for error-correction procedure but because of his larger chip area, the time domain RS decoder is popular currently. To solve this proplem, the nomal basis representation and the conjugate property is utilized. Therefore the chip area can be reduced for the stucture of syndrome delay, nomalization and inverse transform circuit. These modified structures have been implemented using VHDL and synthesized on 0.8${\mu}{\textrm}{m}$ CMOS technology. The results have been compared with other structure for chip area and performance.