Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1998.07f
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- Pages.1902-1904
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- 1998
A Noble Dead Time Minimization Algorithm for Reducing the Swtiching Losses
스위칭 손실저감을 위한 인버터 휴지기간 최소화 알고리즘
- Choi, Jung-Soo (School of Electrical & Computer Engineering, Inha University) ;
- Sin, Jea-Wha (School of Electrical, Inchon junior colledge) ;
- Kim, Young-Seok (School of Electrical & Computer Engineering, Inha University)
- Published : 1998.07.20
Abstract
In this paper. a noble dead time minimization algorithm is presented for reducing the switching losses. Firstly, the effects of the inverter dead time are examined, Secondly the principle of the proposed algorithm is explained with the commutation conditions. And the validity of the proposed algorithm is verified by simulation results. We can conclude from the results that the proposed algorithm have a virtue which is able to reducing the hamonics in the output voltages and which make the output voltage equal to the reference vlaue. Another merit is this method can reduce the number of inverter switchings.
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