한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 1997년도 추계학술대회 논문집
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- Pages.456-460
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- 1997
CMP 공정을 이용한 Multilevel Metal 구조의 평탄화 연구
Planarization of Multi-level metal Structure by Chemical Mechanical Polishing
초록
As device sizes are scaled to submicron dimensions, planarization technology becomes increasing1y important, both during device fabrication and during formation of multilevel interconnects and wiring. Chemical Mechanical Polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. This paper is presented the results of CMP process window characterization studies for 0.35 micron process with 6 metal layers.
키워드