제어로봇시스템학회:학술대회논문집
- 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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- Pages.1485-1488
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- 1997
64MDRAM gate-polysilicon 식각공정의 이상검출에 관한 연구
A study on failure detection in 64MDRAM gate-polysilicon etching process
초록
The capacity of memory chip has increased vert quickly and 64MDRAM becomes main product in semiconductor manufacturing lines consists of many sequential processes, including etching process. although it needs direct sensing of wafer state for the accurae detching, it depends on indirect esnsing and sample test because of the complexity of the plasma etching. This equipment receives the inner light of etch chamber through the viewport and convets it to the voltage inetnsity. In this paper, EDP voltage signal has a new role to detect etching failure. First, we gathered data(EPD sigal, etching time and etchrate) and then analyzed the relationships between the signal variatin and the etch rate using two neural network modeling. These methods enable to predict whether ething state is good or not per wafer. For experiments, it is used High Density Inductive coupled Plasma(HDICP) ethcing equipment. Experiments and results proved to be abled to determine the etching state of wafer on-line and analyze the causes by modeling and EPD signal data.
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