Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1995.11a
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- Pages.299-301
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- 1995
A Circuit Design for Clamping an Overvoltage in Three-level Inverters
3-레벨 인버터를 위한 과전압 제한회로 설계
- Jeong, Jae-Houn (Dept. of Electrical Eng., Hanyang Univ.) ;
- Lee, Yo-Han (Dept. of Electrical Eng., Hanyang Univ.) ;
- Hyun, Dong-Seok (Dept. of Electrical Eng., Hanyang Univ.)
- Published : 1995.11.18
Abstract
This paper represents an overvoltage clamping circuit for three level inverters. With a proposed overvoltage clamping circuit, the problems that high voltage stresses and voltage unbalance between outer and inner switches occurs in high power and high voltage 3-level inverters are reduced.
Keywords