Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Study on the Optimum Design for 3 V CMOS Operational Amplifier with Rail-to-Rail Input Stage and Output Stage

Rail-to-Rail 입력단과 출력단을 갖는 3 V CMOS 연산증폭기의 최적 설계에 관한 연구

  • 박용희 (고려대학교 전기공학과) ;
  • 황상준 (고려대학교 전기공학과) ;
  • 성만영 (고려대학교 전기공학과) ;
  • 김성진 (경남대학교 전자공학과)
  • Published : 1995.07.20
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Abstract

This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.

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