Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Study on the Optimum Design of Balanced CMOS Complementary Folded Cascode OP-AMP

Balanced CMOS Complementary Folded Cascode OP-AMP의 최적설계에 관한 연구

  • 우영신 (고려대학교 전기공학과) ;
  • 배원일 (고려대학교 전기공학과) ;
  • 최재욱 (고려대학교 전기공학과) ;
  • 성만영 (고려대학교 전기공학과)
  • Published : 1995.07.20
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Abstract

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

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