Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1991.07a
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- Pages.166-170
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- 1991
An Advanced On-Resistance Model for Low Voltage VDMOS
저전압 VDMOS 의 ON-저항 모델링
- Kim, Seong-Dong (Seoul National University) ;
- Kim, Il-Jung (Seoul National University) ;
- Choi, Yearn-Ik (Ajou University) ;
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Han, Min-Koo
(Seoul National University)
- Published : 1991.07.18
Abstract
An advanced on-resistance model of VDMOS devices in the low voltage regime is proposed and verified by 2-D device simulations. The model considers the lateral gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping. It is found out that the on-resistance of low voltage VDMOS may be overestimated considerably if it is analyzed by the conventional method. The 2-D device simulation results show that the proposed model is valid for all ranges of cell spacings and breakdown voltages.
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