대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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- Pages.1471-1475
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- 1987
테스트가 용이한 순서 NMOS PLA의 설계
Testable Design of Sequential NMOS PLAs
초록
This paper proposes testable design of sequential NMOS PLAs. The extra bit lines and devices are added to the conventional PLAs. The time is taken to assigning devices in the extra bit lines, which is excessive in the conventional method, is reduced by using the symmetrical distance matrix of the PLA and the regular assigning method. As a result, the test patterns can be easily generated. Also, the silicon area overhead of extra hardware is low.
키워드