Proceedings of the Korean Institute of Communication Sciences Conference (한국통신학회:학술대회논문집)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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RADIX-2 BUTTERFLY 연산회로의 설계

  • 최병윤 (연세대학교 전자공학과) ;
  • 신경욱 (연세대학교 전자공학과) ;
  • 유종근 (연세대학교 전자공학과) ;
  • 임충빈 (연세대학교 전자공학과) ;
  • 김봉열 (연세대학교 전자공학과) ;
  • 이문기 (연세대학교 전자공학과)
  • Published : 1986.04.01
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Abstract

A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.

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