• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• pp.84-87
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• 2010

We manufacture an antifuse OTP (One-time programmable) cell for analog trimming which will be used in power management ICs. For the antifuse cell using dual program voltage of VPP (=7V) and VNN (=-5V), the thin gate oxide is broken down by applying a voltage higher than the hard break-down voltage to the terminals of the antifuse. The area of the manufactured antifuse OTP cell using $0.18{\mu}m$ BCD process is $48.01{\mu}m^2$ and is about 44.6 percent of that of an eFuse cell. The post-program resistances of the antifuse are good with the values under several kilo ohms when we measure twenty test patterns.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.953-958
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• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1858-1864
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• 2009

In this paper, we design a non-volatile memory IP, 1-kb one-time programmable (OTP) memory, used for power management ICs. Since a conventional OTP cell uses an isolated NMOS transistor as an antifuse, there is an advantage of it big cell size with the BCD process. We use, therefore, a PMOS transistor as an antifuse in lieu of the isolated NMOS transistor and minimize the cell size by optimizing the size of a OTP cell transistor. And we add an ESD protection circuit to the OTP core circuit to prevent an arbitrary cell from being programmed by a high voltage between the terminals of the PMOS antifuse when the ESD test is done. Furthermore, we propose a method of turning on a PMOS pull-up transistor of high impedance to eliminate a gate coupling noise in reading a non-programmed cell. The layout size of the designed 1-kb PMOS-type antifuse OTP IP with Dongbu's $0.18{\mu}m$ BCD is $129.93{\times}452.26{\mu}m^2$.

• Journal of the Korean Vacuum Society
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• v.4 no.1
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• pp.46-50
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• 1995

물성을 달리한 $\alpha$-Si을 사용하여 MIM(Metal-Insulator-Metal)구조의 antifuse들을 제작하고, 물성의 변화에 따른 전기적 특성의 변화를 조사하였다. $\alpha$-Si은 PECVD (Plasma Enhanced Chemical Vapor Deposition)방법으로 증착하였으며, 물성은 RF power를 달리하여 변화시켰다. $\alpha$-Si MIM구조의 antifuse를 프로그램할 때 생기는 failure rate를 줄이기 위해 전극 사이에 삽입되는 $\alpha$-Si의 contact hole 크기와 개수를 변화시켜 보았다. MIM antifuse는 contact hole이 2개 이상일 때 failure rate가 10% 이내로 줄었으며, 프로그래밍 전류는 거의 변화가 없었다. 항복전압은 10-11V범위에 집중적으로 분포하였으며, 5V에서의 누설전류는 contact hole의 수가 증가함에 따라 커짐을 알았다.

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.194-199
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• 1997

We fabricated MIM (Metal-Insulator-Metal) antifuses with Al/a-Si/Mo structure and then examined the I-V characteristics and on-state resistance distribution of antifuses. The leakage current of antifuses is below $1Pa/{\mu}m^2$, and programming voltage lies within 10 to 11 V. After programming, on-resistance of antifuses is mostly 10-20$\Omega$ and 20% of these have above 100$\Omega$. In order to reduce on-resistance and the deviation of this distribution, we tried to inject current again into already programed antifuses (we call this re-programming method). From this method, the resistance of antifuses with above 100Ω can be reduced to below 50$\Omega$. When antifuses are programmed by re-programming method, these antifuses have more uniform and lower on-resistance than programmed with one-pulse.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.503-507
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• 2014

The on-state resistance ($R_{ON}$) instability of standard complementary metal-oxide-semiconductor (CMOS) antifuse cells has been observed for the first time by using acceleration factors: stress current and ambient temperature. If the program current is limited, the $R_{ON}$ increases as time passes during read operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.63-69
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• 1995

A novel programming architecture for antifuse FPGA(Field Programmable Gate Array) is described. This architecture prevents programming transistors from breakdown which occurs due to high voltage across the transistors during antifuse programming. Extra mask and processes can be avoided using this proposed architecture. To reduce the applied voltage across the terminals of programming transistors, different voltage ranges are supplied to vertical and horizontal tracks; between programming voltage Vp and Vp/2 for vertical tracks and between Vp/2 and 0V for horizontal tracks. Therefore, Maximum voltage across the programming transistors is half of the programming voltage and an designated antifuse can be programmed by applying maximum voltage for vertical track and minimum voltage for horizontal track while others are subjected to voltage difference below Vp/2.