• Title, Summary, Keyword: XOR Operation

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A Construction of Cellular Array Multiplier Over GF($2^m$) (GF($2^m$)상의 셀배열 승산기의 구성)

  • Seong, Hyeon-Kyeong;Kim, Heung-Soo
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.4
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    • pp.81-87
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    • 1989
  • A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

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Data Hiding in Halftone Images by XOR Block-Wise Operation with Difference Minimization

  • Yang, Ching-Nung;Ye, Guo-Cin;Kim, Cheon-Shik
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.2
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    • pp.457-476
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    • 2011
  • This paper presents an improved XOR-based Data Hiding Scheme (XDHS) to hide a halftone image in more than two halftone stego images. The hamming weight and hamming distance is a very important parameter affecting the quality of a halftone image. For this reason, we proposed a method that involves minimizing the hamming weights and hamming distances between the stego image and cover image in $2{\times}2$-pixel grids. Moreover, our XDHS adopts a block-wise operation to improve the quality of a halftone image and stego images. Furthermore, our scheme improves security by using a block-wise operation with A-patterns and B-patterns. Our XDHS method achieves a high quality with good security compared to the prior arts. An experiment verified the superiority of our XDHS compared with previous methods.

Double Encryption of Binary Image using a Random Phase Mask and Two-step Phase-shifting Digital Holography (랜덤 위상 마스크와 2-단계 위상 천이 디지털 홀로그래피를 이용한 이진 영상 이중 암호화)

  • Kim, Cheolsu
    • Journal of Korea Multimedia Society
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    • v.19 no.6
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    • pp.1043-1051
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    • 2016
  • In this paper, double encryption technique of binary image using random phase mask and 2-step phase-shifting digital holography is proposed. After phase modulating of binary image, firstly, random phase mask to be used as key image is generated through the XOR operation with the binary phase image. And the first encrypted image is encrypted again through the fresnel transform and 2-step phase-shifting digital holography. In the decryption, simple arithmetic operation and inverse Fresnel transform are used to get the first decryption image, and second decryption image is generated through XOR operation between first decryption image and key image. Finally, the original binary image is recovered through phase modulation.

A Design of Cellular Array Parallel Multiplier on Finite Fields GF(2m) (유한체 GF(2m)상의 셀 배열 병렬 승산기의 설계)

  • Seong, Hyeon-Kyeong
    • The KIPS Transactions:PartA
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    • v.11A no.1
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    • pp.1-10
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    • 2004
  • A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

RFID Authentication Protocol Using Shift Operation and Light-weight Operations (Shift연산과 경량 연산자를 사용한 저비용 RFID 인증프로토콜)

  • Ahn, Hyo-Beom;Lee, Su-Youn
    • Convergence Security Journal
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    • v.7 no.1
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    • pp.55-62
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    • 2007
  • In ubiquitous environment the authentication protocol design for RFID security is studied to protect user privacy in RFID system. The XOR-based approach of RFID security is implemented inexpensively and simply. However because of using same security informations, ones of tag is disclosed easily. In this paper, we enhance the previous XOR-based authentication protocol using a circular shift operation.

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An Improvement of Image Encryption using Binary Phase Computer Generated Hologram and Multi XOR Operations (이진위상 컴퓨터형성홀로그램과 다중 XOR 연산을 이용한 영상 암호화의 개선)

  • Kim, Cheol-Su
    • Journal of the Korea Industrial Information Systems Research
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    • v.13 no.3
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    • pp.110-116
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    • 2008
  • In this paper, we proposed an improvement technique of image encryption using binary phase computer generated hologram(BPCGH) and multi exclusive-OR(XOR) operations. For the encryption process, a BPCGH that reconstructs the original image is designed, using an iterative algorithm, and the resulting hologram is regarded as the image to be encrypted. The BPCGH is encrypted through the exclusive-OR operation with the random generated phase key image. Then the encrypted image is divided into several slide images using XOR operations. So, the performance of encryption for the image is improved. For the decryption process, we cascade the encrypted slide images and phase key image and interfere with reference wave. Then decrypted hologram image is transformed into phase information. Finally, the original image is recovered by an inverse Fourier transformation of the phase information. If the slide images are changed, we can get various decrypted BPCGH images. In the proposed security system, without a random generated key image, the original image can not be recovered. And we recover another hologram pattern according to the slide images, so it can be used in the differentiated authorization system.

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XOR-based High Quality Information Hiding Technique Utilizing Self-Referencing Virtual Parity Bit (자기참조 가상 패리티 비트를 이용한 XOR기반의 고화질 정보은닉 기술)

  • Choi, YongSoo;Kim, HyoungJoong;Lee, DalHo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.12
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    • pp.156-163
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    • 2012
  • Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

Techniques for Performance Improvement of Convolutional Neural Networks using XOR-based Data Reconstruction Operation (XOR연산 기반의 데이터 재구성 기법을 활용한 컨볼루셔널 뉴럴 네트워크 성능 향상 기법)

  • Kim, Young-Ung
    • The Journal of The Institute of Internet, Broadcasting and Communication
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    • v.20 no.1
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    • pp.193-198
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    • 2020
  • The various uses of the Convolutional Neural Network technology are accelerating the evolution of the computing area, but the opposite is causing serious hardware performance shortages. Neural network accelerators, next-generation memory device technologies, and high-bandwidth memory architectures were proposed as countermeasures, but they are difficult to actively introduce due to the problems of versatility, technological maturity, and high cost, respectively. This study proposes DRAM-based main memory technology that enables read operations to be completed without waiting until the end of the refresh operation using pre-stored XOR bit values, even when the refresh operation is performed in the main memory. The results showed that the proposed technique improved performance by 5.8%, saved energy by 1.2%, and improved EDP by 10.6%.

Design of an Energy Efficient XOR-XNOR Circuit (에너지 효율이 우수한 XOR-XNOR 회로 설계)

  • Kim, Jeong Beom
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.878-882
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    • 2019
  • XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

Matrix type CRC and XOR/XNOR for high-speed operation in DDR4 and GDDR5 (DDR4/GDDR5에서 고속동작을 위한 matrix형 CRC 및 XOR/XNOR)

  • Lee, JoongHo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.136-142
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    • 2013
  • CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.