• Title, Summary, Keyword: Wafer bonding

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The Behavior of Intrinsic Bubbles in Silicon Wafer Direct Bonding (실리콘 웨이퍼 직접접합에서 내인성 Bubble의 거동에 관한 연구)

  • Moon, Do-Min;Jeong, Hae-Do
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.3
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    • pp.78-83
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    • 1999
  • The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

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Wafer Level Package Using Glass Cap and Wafer with Groove-Shaped Via (유리 기판과 패인 홈 모양의 홀을 갖는 웨이퍼를 이용한 웨이퍼 레벨 패키지)

  • Lee, Joo-Ho;Park, Hae-Seok;Shin, Jea-Sik;Kwon, Jong-Oh;Shin, Kwang-Jae;Song, In-Sang;Lee, Sang-Hun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2217-2220
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    • 2007
  • In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

Bonding Property of Silicon Wafer Pairs with Annealing Method (열처리 방법에 따른 실리콘 기판쌍의 접합 특성)

  • 민홍석;이상현;송오성;주영창
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.5
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    • pp.365-371
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    • 2003
  • We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

Development of The 3-channel Vision Aligner for Wafer Bonding Process (웨이퍼 본딩 공정을 위한 3채널 비전 얼라이너 개발)

  • Kim, JongWon;Ko, JinSeok
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.1
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    • pp.29-33
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    • 2017
  • This paper presents a development of vision aligner with three channels for the wafer and plate bonding machine in manufacturing of LED. The developed vision aligner consists of three cameras and performs wafer alignment of rotation and translation, flipped wafer detection, and UV Tape detection on the target wafer and plate. Normally the process step of wafer bonding is not defined by standards in semiconductor's manufacturing which steps are used depends on the wafer types so, a lot of processing steps has many unexpected problems by the workers and environment of manufacturing such as the above mentioned. For the mass production, the machine operation related to production time and worker's safety so the operation process should be operated at one time with considering of unexpected problem. The developed system solved the 4 kinds of unexpected problems and it will apply on the massproduction environment.

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Development of Automatic Bonding System for GaAs Wafer (GaAs Wafer 접합용 본딩시스템 개발)

  • Song J.Y.;Kang J.H.;Lee C.W.;Ha T.H.;Jee W.H.;Kim W.K.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • pp.427-431
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    • 2005
  • In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

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The Characteristics of the Wafer Bonding between InP Wafers and $\textrm{Si}_3\textrm{N}_4$/InP (Direct Wafer Bonding법에 의한 InP 기판과 $\textrm{Si}_3\textrm{N}_4$/InP의 접합특성)

  • Kim, Seon-Un;Sin, Dong-Seok;Lee, Jeong-Yong;Choe, In-Hun
    • Korean Journal of Materials Research
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    • v.8 no.10
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    • pp.890-897
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    • 1998
  • The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

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Fabrication and Challenges of Cu-to-Cu Wafer Bonding

  • Kang, Sung-Geun;Lee, Ji-Eun;Kim, Eun-Sol;Lim, Na-Eun;Kim, Soo-Hyung;Kim, Sung-Dong;Kim, Sarah Eun-Kyung
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.2
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    • pp.29-33
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    • 2012
  • The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

Reliable Measurement Methodology of Wafer Bonding Strength in 3D Integration Process Using Atomic Force Microscopy (삼차원집적공정에서 원자현미경을 활용한 Wafer Bonding Strength 측정 방법의 신뢰성에 관한 연구)

  • Choi, Eunmi;Pyo, Sung Gyu
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.2
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    • pp.11-15
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    • 2013
  • The wafer bonding process becomes a flexible approach to material and device integration. The bonding strength in 3-dimensional process is crucial factor in various interface bonding process such as silicon to silicon, silicon to metals such as oxides to adhesive intermediates. A measurement method of bonding strength was proposed by utilizing AFM applied CNT probe tip which indicated the relative simplicity in preparation of sample and to have merit capable to measure regardless type of films. Also, New Tool was utilized to measure of tip radius. The cleaned $SiO_2$-Si bonding strength of SPFM indicated 0.089 $J/m^2$, and the cleaning result by RCA 1($NH_4OH:H_2O:H_2O_2$) measured 0.044 $J/m^2$, indicated negligible tolerance which verified the possibility capable to measure accurate bonding strength. And it could be confirmed the effective bonding is possible through SPFM cleaning.

Direct Bonding of GOI Wafers with High Annealing Temperatures (높은 열처리 온도를 갖는 GOI 웨이퍼의 직접접합)

  • Byun, Young-Tae;Kim, Sun-Ho
    • Korean Journal of Materials Research
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    • v.16 no.10
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    • pp.652-655
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    • 2006
  • A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

A Reliability and warpage of wafer level bonding for CIS device using polymer (폴리머를 이용한 CIS(CMOS Image Sensor) 디바이스용 웨이퍼 레벨 접합의 warpage와 신뢰성)

  • Park, Jae-Hyun;Koo, Young-Mo;Kim, Eun-Kyung;Kim, Gu-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.1
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    • pp.27-31
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    • 2009
  • In this paper, the polymer adhesive bonding technology using wafer-level technology was investigated and warpage results were analyzed. Si and glass wafer was bonded after adhesive polymer layer and dam pattern for uniform state was patterned on glass wafer. In this study, warpage result decreased as the low of bonding temperature of Si wafer, bonding pressure and height of adhesive bonding layer. The availability of adhesive polymer bonding was confirmed by TC, HTC, Humidity soak test after dicing. The result is that defect has not found without reference to warpage.

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