• Title, Summary, Keyword: Via hole

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The LED PKG Analysis of Thermal Resistance Characteristics by Following Via hole and FR4 PCB Area (FR4 PCB면적과 Via hole에 따른 LED PKG 열 저항 특성 분석)

  • Kim, Sung-Hyun;Joung, Young-Gi;Park, Dae-Hee
    • Proceedings of the KIEE Conference
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    • pp.1724-1725
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    • 2011
  • 본 논문에서는 LED 패키지의 방열문제를 해결하기 위해 FR4 PCB에 Via-hole을 형성함으로써 열전달 능력을 향상시키고자 하였다. 또한 FR4 PCB의 면적과 Via-hole 크기 및 수량을 변화를 주어 그에 따른 K-factor를 측정 하였으며 열 저항 특성을 분석하였다. 결과로서, Via-hole을 형성한 FR4 PCB의 경우 초기 면적이 증가함에 따라 열 저항 및 접합온도가 급격히 감소하는 특성을 보였으며 200 [mm2]에서 안정화 되는 특성을 보였다. 또한 PCB 면적 및 Via-hole을 형성함에 따라 광 출력이 최대 17% 향상 되었다. 따라서 접합온도 및 열 저항에 있어서 PCB면적의 증가 및 Via-hole을 구성함에 있어 열전달 능력을 향상시킬 수 있음을 확인하였다.

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Study on Reduction of Via hole Pore by Composition variation of Via paste during LTCC Constrained Sintering Process (무수축 LTCC 공정 중 Via Paste의 조성에 따른 Via 주변의 기공감소에 관한 연구)

  • Cho, Hyun-Min;Kim, Jong-Gyu
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.233-234
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    • 2006
  • In this paper, Via hole pore were investigated during PLAS (PessureLess Assisted Constrained Sintering) process of LTCC. Ag and Ag-Pd paste mixture were tested for via paste. Ag paste with 10~25% Ag-Pd paste showed no via hole pore, but further increase of Ag-Pd contents in via paste increased via pore. From shrinkage curve, 10~25% Ag-Pd paste showed expansion behaviors before shrink and this phenomena result in the reduction of via hole pore during PLAS process.

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Study of SI Characteristic of Multilayer PCB with a Through-Hole Via (관통형 비아가 있는 다층 PCB의 SI 성능 연구)

  • Kim, Li-Jin;Lee, Jae-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.2
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    • pp.188-193
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    • 2010
  • In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.

Thickness Effect of Double Layered Sheet on Burr Formation during Micro-Via Hole Punching Process (미세 비아홀 펀칭 공정 중 이종 재료 두께에 따른 버 생성)

  • 신승용;임성한;주병윤;오수익
    • Transactions of Materials Processing
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    • v.13 no.1
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    • pp.65-71
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    • 2004
  • Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole qualify is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene terephthalate) one. In this paper we found the correlation between hole quality and process condition such as PET thickness and ceramic thickness. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

Mechanical Reliability Issues of Copper Via Hole in MEMS Packaging (MEMS 패키징에서 구리 Via 홀의 기계적 신뢰성에 관한 연구)

  • Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.2
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    • pp.29-36
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    • 2008
  • In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

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Analysis of Thermal Properties in LED Package by Via-hole and Dimension of FR4 PCB (FR4 PCB면적과 Via-hole이 LED패키지에 미치는 열적 특성 분석)

  • Kim, Sung-Hyun;Lee, Se-Il;Yang, Jong-Kyung;Park, Dae-Hee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.3
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    • pp.234-239
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    • 2011
  • In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

The Analysis of Thermal & Optical Properties in LED Package by the PCB structure and via hole formation (PCB 구조와 via hole 구성에 따른 LED 패키지의 열적 광학적 특성 분석)

  • Lee, Se-Il;Lee, Seung-Min;Yang, Jong-Kyung;Park, Hyung-Jun;Park, Dae-Hee
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.297-298
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    • 2009
  • 대부분의 반도체 소자의 고장 원인은 85%정도가 열로 인한 것이며, 고출력 LED는 인가된 에너지의 20%정도의 광으로 출력되며 나머지 80%가 열로 전환된다. 본 논문에서는 PMS-50과 KEITHLEY 2430을 이용하여 PCB 구조와 Via hole 구성에 따른 LED 패키지의 열적 광학적 특성을 분석하였다. 0.6mm의 Via hole을 가진 FR4 PCB의 열특성이 가장 우수하였으며, Via hole 0.6mm FR4 PCB의 경우 McPCB에 상응하는 광출력 특성을 보였다.

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Improved Characteristic of Radiated Emission of a PCB by Using the Via-Hole Position (단일 비아 위치를 이용한 PCB의 복사성 방사 성능 향상)

  • Kim, Li-Jin;Lee, Jae-Hyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.12
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    • pp.1272-1278
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    • 2009
  • The cancellation method of P/G(power/ground) plane resonances which are generated between the power plane and the ground plane in a 4-layer PCB(Printed Circuit Boards) with a via-hole for the improvement of the RE(Radiated Emission) characteristic is presented. The validity of the proposed method was confirmed from simulation and measurement of performances of signal transmission characteristic, intensities of edge-radiation and radiated emission of PCB with a via-hole.

A Via-Hole Process for GaAs MMIC's using Two-Step Dry Etching (2단계 건식식각에 의한 GaAs Via-Hole 형성 공정)

  • 정문식;김흥락;이지은;김범만;강봉구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.1
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    • pp.16-22
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    • 1993
  • A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

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Empirical Model of Via-Hole Structures in High-Count Multi-Layered Printed Circuit Board (HCML 배선기판에서 비아홀 구조에 대한 경험적 모델)

  • Kim, Young-Woo;Lim, Yeong-Seog
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.12
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    • pp.55-67
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    • 2010
  • The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.