• Title, Summary, Keyword: Synthesis

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Optimum MVF Estimation-Based Two-Band Excitation for HMM-Based Speech Synthesis

  • Han, Seung-Ho;Jeong, Sang-Bae;Hahn, Min-Soo
    • ETRI Journal
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    • v.31 no.4
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    • pp.457-459
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    • 2009
  • The optimum maximum voiced frequency (MVF) estimation-based two-band excitation for hidden Markov model-based speech synthesis is presented. An analysis-by-synthesis scheme is adopted for the MVF estimation which leads to the minimum spectral distortion of synthesized speech. Experimental results show that the proposed method significantly improves synthetic speech quality.

Recovery of RNA Synthesis After Ultraviolet Irradiation of Xeroderma Pigmentosum Group F and G (색소성 건피증 세포 F, G군의 자외선 조사 후 RNA 합성 회복에 관한 연구)

  • 장해룡
    • Toxicological Research
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    • v.15 no.1
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    • pp.35-38
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    • 1999
  • RNA synthesis rate was measured at different time points after UV irradiation in various xeroderma pigmentosum (XP) cells including complementation groups F and G. The RNA synthesis was assayed by measuring 3H-uridine incorporation. In normal cells, recovery of RNA synthesis was initiated at about 6 hr ager UV irradiation and reached to the same level as in unirradiated cells at 24hr after UV irradiation. By contrast, no such recovery was observed in group F,G XP cells.

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A Study on the area minimization using general floorplan (종합평면을 사용한 면적 최적화에 관한 연구)

  • 이용희;정상범이천희
    • Proceedings of the IEEK Conference
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    • pp.1021-1024
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    • 1998
  • Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

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A Study on High-Level Pipeline Synthesis System: Data Path Synthesis and Control Synthesis (상위수준 파이프라인 합성시스템에 관한 연구: 데이트 경로 및 콘트롤 합성)

  • Kim, Jong-Tae
    • Journal of the Korean Society of Industry Convergence
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    • v.3 no.4
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    • pp.299-306
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    • 2000
  • 이 논문은 파이프라인 함성을 위한 상위수준 데이터 경로 하성과 콘트롤 합성의 통합에 관한 연구이다. 현재 대부분의 상위수준 합성 방법은 콘트롤 영역의 영향을 무시하는데 보다 나은 설계를 위하여 데이터 경로디자인 영역과 콘트롤 디자인 영역을 통합하여 탐색하는 파이프라인 상위수준함성 도구를 구현했다. 이 도구는 비용 제한 하에서 최고 성능의 파이프라인을 합성하는 비용재한합성과 성능 제한 하에서 최서 비용의 파이프라인을 합성하는 성능 제한합성의 두 가지 방식을 제공한다.

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Transformation from asynchronous finite state machines to signal transition graphs for speed-independent circuit synthesis (속도 독립 회로 합성을 위한 비동기 유한 상태기로부터 신호전이 그래프로의 변환)

  • 정성태
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.195-204
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    • 1996
  • We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

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