• Title, Summary, Keyword: Refresh time

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The effect of GIDL and SILC on the performance degradation of the refresh circuit in DRAM (GIDL과 SILC가 DRAM refresh 회로의 성능저하에 미치는 영향)

  • 이병진;윤병오;홍성희;유종근;전석희;박종태
    • Proceedings of the IEEK Conference
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    • pp.429-432
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    • 1998
  • The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

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A Pre-Refresh Technique for Improving DRAM Performance (DRAM의 성능 향상을 위한 Pre-Refresh 기법)

  • Cho, Minshin;Han, Kyong-Ho;Jang, Wooyoung
    • The Journal of Korean Institute of Information Technology
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    • v.16 no.10
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    • pp.27-35
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    • 2018
  • Dynamic random access memory (DRAM) latency depends on the row activation time required to detect the charge of a DRAM cell. If a DRAM cell is fully charged, the sense amplifier can rapidly detect charges, thus reduce the row activation time. In this paper, we propose a pre-refresh technique to reduce the row activation time of DRAM. The pre-refresh technique charges DRAM cells in a row that are expected to be accessed while DRAM is idle. If any DRAM cells in the row are read or written soon, the row activation time can be reduced. Experimental results show that, when the pre-refreshed quad-core processor performs PARSEC benchmarks, a memory system with the pre-refresh technique causes 5.49% less power consumption, and achieves 11.8% faster program execution time.

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

  • Lee, Jung-Hwan;Jeon, Seong-Do;Chang, Sung-Keun
    • ETRI Journal
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    • v.26 no.6
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    • pp.583-588
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    • 2004
  • In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

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Implementation of Self-Refresh Clock Generation Circuit for Mobile 1T Memory Using Time-Digital Converter (시간-디지털 변환기를 이용한 모바일 1T 메모리용 자가-리프레쉬 클록 생성회로 구현)

  • Won, Da-Sol;Kim, Jin-Won;Choi, Ho-Yong
    • The Journal of Korean Institute of Information Technology
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    • v.15 no.12
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    • pp.61-68
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    • 2017
  • In this paper, we propose a self-refresh clock generator for mobile memory using a time-digital converter (TDC). The circuit consists of a temperature sensor to convert temperature to digital data and a refresh clock generator circuit that outputs a refresh clock in accordance with temperature region. The temperature sensor consists of a temperature-pulse converter (TPC) using a chain of inverters with the same size and a TDC that converts it to 9-bit digital data using a reference oscillator. In the refresh clock generating circuit, the converted digital data is divided into five regions, and a clock corresponding to the data region is generated. Implementation results using a $0.18{\mu}m$ CMOS process show that it is possible to generate variable clocks by dividing the temperature of $-40^{\circ}C{\sim}100^{\circ}C$ into 5 regions, the chip area is $0.124mm^2$, and the power consumption is 1.5mW. Compared with the conventional refresh clock circuit using BGR and ADC, the chip area is improved to 32% and the power consumption is improved to 72%.

An Effective Pre-refresh Mechanism for Embedded Web Browser of Mobile Handheld Devices

  • Li Huaqiang;Kim Young-Hak;Kim Tae-Hyung
    • Journal of Korea Multimedia Society
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    • v.7 no.12
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    • pp.1754-1764
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    • 2004
  • Lately mobile handheld devices such as Personal Digital Assistant (PDA) and cellular phones are getting more popular for personal web surfing. However, today most mobile handheld devices have relatively poor web browsing capability due to their low performance so their users have to suffer longer communication latency than those of desktop Personal Computers (PCs). In this paper, we propose an effective pre-refresh mechanism for embedded web browser of mobile handheld devices to reduce this problem. The proposed mechanism uses the idle time to pre-refresh the expired web objects in an embedded web browser's cache memory. It increases the utilization of Central Processing Unit (CPU) power and network bandwidth during the idle time and consequently reduces the client's latency and web browsing cost. An experiment was done using a simulator designed by us to evaluate the efficacy of the proposed mechanism. The experiment result demonstrates that it has a good performance to make web surfing faster.

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Bitrate Adaptive Intra Refresh for MPEG-4 Video (MPEG-4 비디오에서의 비트율 적응 인트라 리프레쉬)

  • 금찬헌;최동환;황찬식
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.4
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    • pp.23-30
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    • 2004
  • In MPEG-4 video, Motion Adaptive Intra Refresh (MAIR) encodes a motion area macroblock in intra mode, thereby preventing the error propagation. Motion area is selected by difference of between current macroblock and previous macroblock. An effective implementation of the AIR is to reduce the maximum refresh time and estimate the error prone macroblock. However in the case or the MAIR, unnecessary macroblock can be encoded in intra mode. in this paper, a bitrate AIR is proposed that reduces the maximum refresh time by estimating the error prone macroblock more efficiently.

Optimizing Mobile Advertising Using Ad Refresh Interval

  • Truong, Vinh
    • IEIE Transactions on Smart Processing and Computing
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    • v.5 no.2
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    • pp.117-122
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    • 2016
  • Optimizing the number of ad clicks is a large-scale learning problem that is central to the multi-billion dollar mobile advertising industry. There are currently several optimization methods used, including ad mediation and ad positioning. This paper proposes a new method to optimize mobile advertising by using the ad refresh interval. A new metric, which can measure and compare mobile advertising performance, takes into account time limitations. The results achieved from this optimization study could maximize revenue for mobile advertisers and publishers. This research has high applicability. It also lays out a solid background for future research in this promising area.

CMOS On-Chip Temperature detector circuit For Low Power DRAM (저전력 DRAM을 위한 온-칩 온도 감지 회로)

  • Kim, Young-Sik;Lee, Jong-Seok;Yang, Ji-Un;Lee, Hyun-Seok;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • pp.232-234
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    • 1996
  • The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

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Techniques to improve DRAM Energy Efficiency through Selective Refresh (선택적 리프레시를 통한 DRAM 에너지 효율 향상 기법)

  • Kim, Young-Ung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.2
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    • pp.179-185
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    • 2020
  • DRAM is a major component of the main memory system. As the operating system evolves and application complexity and capacity increases, the capacity and speed of DRAM are also increasing. DRAM should perform a refresh action of periodically reading and then re-storing stored values, and the accompanying performance and power/energy overhead embodies characteristics that worsen as capacity increases. This study proposes an energy efficiency improvement technique that efficiently stores the rows that need to be refreshed within 64ms and 128ms using the bloom filter for cells with the lowest retention time of electrons. The results of the experiment showed that the proposed technique resulted in an average 5.5% performance improvement, 76.4% reduction in average refresh energy, and 10.3% reduction in average EDP.

Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell (평면구조 P-MOS DRAM 셀의 커패시터 VT 이온주입의 최적화)

  • Chang Sung-Keun;Kim Youn-Jang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.2
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    • pp.126-129
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    • 2006
  • We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.