• Title, Summary, Keyword: Rapid thermal annealing

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Rapid thermal annealing effect of IZO transparent conducting oxide films grown by a box cathode sputtering (박스캐소드 스퍼터로 성장시킨 IZO 투명 전도막의 급속 열처리 효과)

  • Bae, Jung-Hyeok;Moon, Jong-Min;Jeong, Soon-Wook;Kim, Han-Ki;Yi, Min-Soo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.473-474
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    • 2006
  • We report on the rapid thermal annealing effect on the electrical, optical, and structural properties of IZO transparent conducting oxide films grown by box cathode sputtering (BCS). To investigate structural properties of rapid thermal annealed IZO films in $N_2$ atmosphere as a function of annealing temperature, syncrotron x-ray scattering experiment was carried out. It was shown that the amorphous structure of the IZO films was maintained until $400^{\circ}C$ because ZnO and $In_2O_3$ are immiscible and must undergo phase separation to allow crystallization. In addition, the IZO films grown at different Ar/$O_2$ ratio of 30/1.5 and 30/0 showed different preferred (222) and (440) orientation, respectively, with increase of rapid thermal annealing temperature. The electrical properties of the OLED with rapid thermal annealed IZO anode was degraded as rapid thermal annealing temperature of IZO increased. This indicates the amorphous IZO anode is more beneficial to make high-quality OLEDs.

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Rapid Thermal Annealing of GaN EpiLayer grown by Molecular Beam Epitaxy (MBE로 성장한 GaN 에피층의 급속 열처리)

  • Choi, Sung-Jai;Lee, Won-Sik
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.1
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    • pp.7-13
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    • 2010
  • We have investigated effects of the rapid thermal annealing of GaN epilayers by molecular beam epitaxy in nitrogen atmosphere. The improvement of structural properties of the samples was observed after rapid thermal annealing under optimum conditions. This improvement in crystal quality is due to a reduction of the spread in the lattice parameter in epilayers. The annealing has been performed in a rapid thermal annealing furnace at $950^{\circ}C$. The effect of rapid thermal annealing on the structural properties of GaN was studied by x-ray diffraction. The Bragg peak shifts toward larger angle as the annealing time increases. As the thermal treatment time increases, FWHM(full width at half maximum) of the peak slightly increase with its decreases followed and it increases again. Results demonstrate that rapid thermal annealing did not always promote qualities of GaN epilayers. However, rapid thermal annealing under optimum conditions improve structural properties of the samples, elevating their crystal quality with a reduction of inaccuracy in the lattice parameter of the epilayers.

Effect of rapid thermal annealing of GaN EpiLayer (GaN 에피층의 급속 열처리 효과)

  • Choi, Sung Jai;Lee, Won Sik
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.8 no.6
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    • pp.105-110
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    • 2008
  • We have investigated the high temperature rapid thermal annealing of GaN epilayers in nitrogen atmosphere. Annealing has been performed in a rapid thermal annealing furnace at $950^{\circ}C$. The effect of rapid thermal annealing of GaN was studied by x-ray diffraction. The Bragg peak shifts toward larger angle as the annealing time increases. The full width at half maximum (FWHM) of the peak slightly increase, followed by decreases, and increases again as the thermal treatment time increases. The improvement of structural properties of the samples was observed after rapid thermal annealing under optimum conditions. This improvement in crystal quality is due to a reduction of the spread in the lattice parameter in epilayers.

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Application of Modified Rapid Thermal Annealing to Doped Polycrystalline Si Thin Films Towards Low Temperature Si Transistors

  • So, Byung-Soo;Kim, Hyeong-June;Kim, Young-Hwan;Hwang, Jin-Ha
    • Korean Journal of Materials Research
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    • v.18 no.10
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    • pp.552-556
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    • 2008
  • Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

Structural evolution and electrical property of RF sputter-deposited ZnO:Al film by rapid thermal annealing process (RF sputter로 증착된 ZnO:Al 박막의 Rapid Thermal Annealing 처리에 따른 구조개선 및 전기적 특성)

  • Park, Kyeong-Seok;Lee, Kyu-Seok;Lee, Sung-Wook;Park, Min-Woo;Kwak, Dong-Joo;Lim, Dong-Gun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.466-467
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    • 2005
  • Al doped zinc oxide films (ZnO:Al) were deposited on glass substrate by RF magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The as-deposited ZnO:Al films were rapid-thermal annealed. Electrical properties and structural evolution of the films, as annealed by rapid thermal process (RTP), were studied and compared with the films annealed by conventional annealing process. RTP, the (002) peak intensity increases and the electrical resistivity decreases by 20%, after RT annealing. The effects of RT annealing on the structural evolution and electrical properties of RF sputtered films were further discussed and compared also with the films deposited by DC magnetron sputtering.

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Stress Evolution with Annealing Methods in SOI Wafer Pairs (열처리 방법에 따른 SOI 기판의 스트레스변화)

  • Seo, Tae-Yune;Lee, Sang-Hyun;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.12 no.10
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    • pp.820-824
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    • 2002
  • It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

Effect of Rapid Thermal Annealing and Orientation of Si Substrate on Structural and Electrical Properties of MOCVD-grown TiO2 Thin Films (급속 후 열처리 및 실리콘기판 배향에 따른 MOCVD-TiO2박막의 구조적.전기적 특성)

  • 왕채현;최두진
    • Journal of the Korean Ceramic Society
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    • v.35 no.1
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    • pp.88-96
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    • 1998
  • The structural and electrical properties of titanium dioxide(TiO2) thin films deposited on p-type (100) si and 4$^{\circ}$off(100) Si substartes by metalorganic chemical vapor deposition (MOCVD) have been studied with post rapid thermal annealing. TiO2 thin films of anatase phase were grown at 300-500$^{\circ}C$ using titanium post rapid thermal annealing at a temperature of 800$^{\circ}C$ for 30sec. rutile phase was observed in the condition of the deposition temperature over 350$^{\circ}C$ in the ambient air atmosphere and at 500$^{\circ}C$ in cacuu,. SEM and AFM study show-ed surface roughness were increased slightly from 40${\AA}$to 55${\AA}$ after annealing due to grain growth and phase transformation. From capacitane-voltage measurement of Al/TiO2./p-Si structure after annealing we obtained ideal capacitance-voltage characteristics of MOS structure with dielectric constant of 16-22 in case of (100) Si and about 30- in case of 4$^{\circ}$off(100) Si but showed the higher leakage current.

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Comparison of shallow junction properties depending on ion implantation and annealing conditions (이온주입 및 열처리 조건에 따른 박막접합의 특성 비교)

  • 홍신남;김재영
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.7
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    • pp.94-101
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    • 1998
  • To form 0.2 .mu.m p$^{+}$-n junctions, BF$_{2}$ ions with the energy of 20keV and the dose of 2*10$^{15}$ cm$^{-2}$ were implanted into the crystalline and preamorphized silicon substrates. Th epreamorphization was performed using 45keV, 3*10$^{14}$ cm$^{-2}$ As or Ge ions. Th efurnace annealing and rapid thermal annealing were empolyed to annihilate the implanted damage and to activate the implanted boron ions.The junction properties were analyzed with the measured values of the junction depth, sheet resistances, residual defects, and leakage currents. The thermal cycle of furnace annela followed by rapid thermal annela shows better characteristics than the annealing sequence of rapid thermal anneal and furnace annela.Among the premorphization species, Ge ion exhibited the better characteristics than the As ion.n.

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Rapid thermal annealing to minimize Slip (슬립현상을 최소화 하기위한 급속열처리)

  • Kwon, Kyung-Sup;Lee, Byum-Hak;Hwang, Ho-Jung
    • Proceedings of the KIEE Conference
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    • pp.375-378
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    • 1988
  • In this paper a newly designed rapid thermal process (RTP) structure is proposed to the slip induced in silicon wafers considerably. The reflectors and a graphite radiation were used to compensate the temperature difference causing slip in silicon wafers. From our experiments it is known that slip can be removed during a rapid thermal annealing at high temperature.

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