• Title, Summary, Keyword: Planar P-MOS

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Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell (평면구조 P-MOS DRAM 셀의 커패시터 VT 이온주입의 최적화)

  • Chang Sung-Keun;Kim Youn-Jang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.2
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    • pp.126-129
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    • 2006
  • We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

Conducting Polymer Material Characterization Using High Frequency Planar Transmission Line Measurement

  • Cho, Young-Seek;Franklin, Rhonda R.
    • Transactions on Electrical and Electronic Materials
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    • v.13 no.5
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    • pp.237-240
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    • 2012
  • A conducting polymer, poly 3-hexylthiophene (P3HT) is characterized with the metal-insulator-semiconductor (MIS) measurement method and the high frequency planar circuit method. From the MIS measurement method, the relative dielectric constant of the P3HT film is estimated to be 4.4. For the high frequency planar circuit method, a coplanar waveguide is fabricated on the P3HT film. When applying +20 V to the CPW on P3HT film, the P3HT film is in accumulation mode and becomes lossy. The CPW on P3HT film is 1.5 dB lossier than the CPW on $SiO_2$ film without P3HT film at 50 GHz.

Characterization and Comparison of Doping Concentration in Field Ring Area for Commercial Vertical MOSFET on 8" Si Wafer (8인치 Si Power MOSFET Field Ring 영역의 도핑농도 변화에 따른 전기적 특성 비교에 관한 연구)

  • Kim, Gwon Je;Kang, Ye Hwan;Kwon, Young-Soo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.4
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    • pp.271-274
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    • 2013
  • Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.