• Title, Summary, Keyword: PLL

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New 3-Phase Phase Locked Loop(PLL) Strategy Haying Frequency Limiter and Anti-windup Suitable to Uninterruptible Power Supply (무정전전원장치에 적합한 주파수 제한기와 안티 와인드업을 가지는 새로운 3상 전원각 정보 추출 방식)

  • Ji, Jun-Keun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.7 no.6
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    • pp.1086-1091
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    • 2006
  • In this paper an advanced PLL strategy suitable to UPS, compared with conventional PLL strategy using the positive sequence component extracted from source voltages, is suggested. Frequency limiter and anti-windup are added to conventional PI controller in suggested PLL strategy. Basic operational principle of suggested PLL is same as that of conventional PLL, but the difference between two strategies is that the suggested PLL can limit the change of frequency in constant range because of inclusion of frequency limiter. Compute. simulation was carried fer the DVR(dynamic voltage restorer) compensating voltage to examine the difference between conventional PLL strategy and the suggested PLL strategy limiting frequency. And the results clearly demonstrate the effectiveness of the suggested PLL strategy for UPS.

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A Fast Lock and Low Jitter Phase Locked Loop with Locking Status Indicator (Locking 상태 표시기를 이용한 저잡음 고속 위상고정 루프)

  • Choi Young-Shig;Han Dae-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.3
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    • pp.582-586
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    • 2005
  • This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

A Robust PLL Technique Based on the Digital Lock-in Amplifier under the Non-Sinusoidal Grid Conditions (디지털 록인앰프를 이용한 비정현 계통하에서 강인한 PLL 방법)

  • Ashraf, Muhammad Noman;Khan, Reyyan Ahmad;Choi, Woojin
    • Proceedings of the KIPE Conference
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    • pp.104-106
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    • 2018
  • The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

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A Study on PLL Design for Ultra Wideband (초 광대역용 PLL 설계에 관한 연구)

  • Lee, Yong-Woo;Lee, Il-Kyoo;Oh, Seung-Hyeub
    • The Journal of The Institute of Internet, Broadcasting and Communication
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    • v.10 no.4
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    • pp.193-198
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    • 2010
  • In this paper, we have introduced a new way to have low phase noise PLL of the Ultra wideband to meet performance requirements. Before development of the PLL, we simulated spectrum power, phase noise by using ADS. Finally, we confirm a satisfying result between required standard and measured value.

A New Phase Locked Loop(PLL) Strategy Suitable to UPS (무정전전원장치에 적합한 새로운 전원각 정보 추출 기술)

  • Ji Jun-Keun
    • Proceedings of the KAIS Fall Conference
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    • pp.198-202
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    • 2004
  • 본 논문에서는 전력 품질 기기의 제어에 있어서 필수적 요소라고 할 수 있는 전원각을 찾는 방법 중에서 PLL에 관하여 기존의 방식들을 먼저 알아보고, UPS 시스템에 적용하기에 적합한 새로운 PLL 방식을 제안하며, 컴퓨터 시뮬레이션을 통해 기존의 방식과의 성능 비교를 통해서 제안된 새로운 PLL 방식의 우수성을 입증한다. 본 논문에서는 기존의 정상분을 추출하여 이용하는 PLL 방식을 UPS에 적합한 형태로 개선한 주파수를 제안한 PLL 방식을 제안하였다. 이 PLL 방식은 기존의 PI 제어기에 주파수 제한기(limiter)와 안티 와인드업(anti-wind up)을 추가하였다. 이것의 기본적인 동작 원리는 기존의 방법들과 같지만, 차이점은 주파수 제한기의 삽입으로 인하여 주파수 변동률을 일정한 범위 내에서 제한할 수 있다는 것이다. 기존의 PLL 방법과 본 논문에서 제안된 주파수를 제한한 PLL 방법의 차이를 알아보기 위하여 동적 전압 보상기로 전압을 보상하는 시뮬레이션을 하였고, 결과적으로 제안된 주파수를 제한한 PLL 방법이 기존의 PLL 방법보다 UPS에 적합함을 입증하였다.

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Communication Performance Analysis and Characteristics of Frequency Synthesizer in the OFDM/FH Communication System (OFDM/FH 통신시스템에 사용되는 주파수 합성기의 특성과 통신 성능 분석)

  • 이영선;유흥균
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.8
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    • pp.809-815
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    • 2003
  • It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

A PLL Controller for Unbalanced Grid Voltage (전압 불평형 계통을 위한 PLL 제어기)

  • Lee, Chi Hwan
    • Proceedings of the KIPE Conference
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    • pp.43-44
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    • 2013
  • 정상분과 역상분의 전압이 존재하는 삼상 계통의 전압 불평형은 dq 변환에서 맥동전압 성분을 발생시킨다. 인버터의 동작을 위한 PLL의 위상 추적 능력은 맥동 전압에 의해 감소하게 된다. 정상분과 역상분의 분리를 통해 맥동 성분의 제거가 가능하지만 복잡한 PLL 구성을 갖는다. 본 연구는 불평형 상태에서 발생하는 dq 성분의 주파수가 기본파의 짝수 배만 존재하는 성질을 이용하여 comb 필터를 PLL 제어기에 적용하였다. 전압 불평형 및 고조파 성분에 대해서도 맥동 없는 dq 전압 획득이 가능하다. 기본 PLL 제어기에 단순 시간지연의 comb 필터로 견실한 PLL 제어기가 얻어진다. 제안된 PLL 제어기는 시뮬레이션으로 성능을 확인하였다.

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A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions (비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법)

  • Khan, Reyyan Ahmad;Choi, Woojin
    • The Transactions of the Korean Institute of Power Electronics
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    • v.23 no.4
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    • pp.231-239
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    • 2018
  • The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions (비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법)

  • Khan, Reyyan Ahmad;Ashraf, Muhammad Noman;Choi, Woojin
    • Proceedings of the KIPE Conference
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    • pp.7-8
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    • 2017
  • The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

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PLL Strategy Hating Frequency Limiter and Anti-windup Suitable to UPS (무정전전원장치에 적합한 주파수 제한기와 안티 와인드업을 가지는 PLL 방식)

  • Ji Jun-Keun;Kim Hyo-sung;Sul Seung-Ki;Kim Kyung-Hwan
    • Proceedings of the KIPE Conference
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    • pp.778-782
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    • 2004
  • 본 논문에서는 전력 품질 기기의 제어에 있어서 필수적 요소라고 할 수 있는 전원각을 찾는 방법중에서 PLL(Phase Locked Loop)에 관하여 기존의 방식들을 먼저 알아보고, 정상분을 추출하여 이용하는 기존의 PLL 방식을 무정전전원장치에 적합한 형태로 개선한 주파수를 제한한 PLL 방식을 제안하였다. 제안된 PLL 방식은 기존의 PI 제어기에 주파수 제한기(limiter)와 안티 와인드업(anti-windup)을 추가하였다. 이것의 기본적인 동작 원리는 기존의 방법들과 같지만, 차이점은 주파수 제한기의 삽입으로 인하여 주파수 변동률을 일정한 범위 내에서 제한할 수 있다는 것이다. 기존의 PLL 방법과 본 논문에서 제안된 주파수를 제한한 PLL 방법의 차이를 알아보기 위하여 동적 전압 보상기로 전압을 보상하는 시뮬레이션을 하였고, 결과적으로 제안된 주파수를 제한한 PLL 방법이 기존의 PLL 방법보다 UPS에 적합함을 입증하였다.

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