• Title, Summary, Keyword: P-MOS DRAM cell

Search Result 3, Processing Time 0.04 seconds

Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell (평면구조 P-MOS DRAM 셀의 커패시터 VT 이온주입의 최적화)

  • Chang Sung-Keun;Kim Youn-Jang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.19 no.2
    • /
    • pp.126-129
    • /
    • 2006
  • We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

The Electrical Characteristics of SRAM Cell with Stacked Single Crystal Silicon TFT Cell (단결정 실리콘 TFT Cell의 적용에 따른 SRAM 셀의 전기적 특성)

  • Lee, Deok-Jin;Kang, Ey-Goo
    • Journal of the Korea Computer Industry Society
    • /
    • v.6 no.5
    • /
    • pp.757-766
    • /
    • 2005
  • There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

  • PDF

Electrical Characteristics of SRAM Cell with Stacked Single Crystal Silicon TFT Cell (Stacked Single Crystal Silicon TFT Cell의 적용에 의한 SRAM 셀의 전기적인 특성에 관한 연구)

  • Kang, Ey-Goo;Kim, Jin-Ho;Yu, Jang-Woo;Kim, Chang-Hun;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.19 no.4
    • /
    • pp.314-321
    • /
    • 2006
  • There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.