• Title, Summary, Keyword: Metastability Window

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Mesochronous Clock Based Synchronizer Design for NoC (위상차 클럭 기반 NoC 용 동기회로 설계)

  • Kim, Kang-Chul;Chong, Jiang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.10
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    • pp.1123-1130
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    • 2015
  • Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

Metastability Window Measurement of CMOS D-FF Using Bisection (이분법을 이용한 CMOS D-FF의 불안정상태 구간 측정)

  • Kim, Kang-Chul;Chong, Jiang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.2
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    • pp.273-280
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    • 2017
  • As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

Metastability-free Mesochronous Synchronizer for Networks on Chip (불안정 상태를 제거한 NoC용 위상차 클럭 동기회로)

  • Kim, Kang-Chul
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.6
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    • pp.1242-1249
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    • 2012
  • This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.