• Title, Summary, Keyword: Junctionless

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Comparative Analysis of PBTI Induced Device Degradation in Junctionless and Inversion Mode Multiple-Gate MOSFET (PBTI에 의한 무접합 및 반전모드 다중게이트 MOSFET의 소자 특성 저하 비교 분석)

  • Kim, Jin-Su;Hong, Jin-Woo;Kim, Hye-Mi;Lee, Jae-Ki;Park, Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.151-157
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    • 2013
  • In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

Development of Gate Structure in Junctionless Double Gate Field Effect Transistors (이중게이트 구조의 Junctionless FET 의 성능 개선에 대한 연구)

  • Cho, Il Hwan;Seo, Dongsun
    • Journal of IKEEE
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    • v.19 no.4
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    • pp.514-519
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    • 2015
  • We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors (나노와이어 junctionless 트랜지스터의 문턱전압 및 평탄전압 모델링과 소자설계 가이드라인)

  • Kim, Jin-Young;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.1-7
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    • 2011
  • In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

Electrical Coupling of Monolithic 3D Inverter Consisting of Junctionless FET (Junctionless FET로 구성된 적층형 3차원 인버터의 전기적 상호작용에 대한 연구)

  • Jang, Ho-Yeong;Kim, Kyung-won;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.614-615
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    • 2016
  • I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

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Investigation of Junctionless Transistors for High Reliability

  • Jeong, Seung-Min;O, Jin-Yong;Islam, M. Saif;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • pp.142-142
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    • 2012
  • 최근 반도체 산업의 발전과 동시에 소자의 집적화에 따른 단채널 효과가 문제되고 있다. 채널 영역에 대한 게이트 영역의 제어능력이 떨어지면서 누설전류의 증가, 문턱전압의 변화가 발생하며, 이를 개선하기 위해 이중게이트 혹은 다중게이트 구조의 트랜지스터가 제안되었다. 하지만 채널길이가 수십나노미터 영역으로 줄어듦에 따라 소스/드레인과 채널간의 접합형성이 어렵고, 고온에서 열처리 과정을 거칠 경우 채널의 유효길이를 제어하기 힘들어진다. 최근에 제안된 Junctionless 트랜지스터의 경우, 소스/드레인과 채널간의 접합이 없기 때문에 접합형성 시 발생하는 공정상의 문제뿐만 아니라 누설전류영역을 개선하며, 기존의 CMOS 공정과 호환되는 이점이 있다. 한편, 집적화되는 반도체 기술에 따라, 동작 시 발생하는 스트레스가 소자의 신뢰성에 중요한 요인으로 작용하게 되며, 현재 Junctionless 트랜지스터의 신뢰성 특성에 관한 연구가 부족한 상황이다. 따라서, 본 연구에서는 Junctionless 트랜지스터의 NBTI 특성과 hot carrier effect에 의한 신뢰성 특성을 분석하였다. Junctionless 트랜지스터의 경우, 축적모드로 동작하기 때문에 스트레스에 의해 유기되는 캐리어의 에너지가 낮다. 그 결과, 반전모드로 동작하는 Junction type의 트랜지스터에 비해 스트레스에 의한 subthreshold swing 기울기의 열화와 문턱전압의 이동이 감소하였다. 또한 소스/드레인과 채널간의 접합이 없기 때문에 hot carrier effect에 의한 게이트 절연막 및 계면에서의 열화가 개선되었다.

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Steep subthreshold slope at elevated temperature in junctionless and inversion-mode MuGFET (고온에서 무접합 및 반전모드 MuGFET의 문턱전압 이하에서 급격히 작은 기울기 특성)

  • Lee, Seung-Min;Park, Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.9
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    • pp.2133-2138
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    • 2013
  • In this paper, the variation of a steep subthreshold slope at elevated temperature in nanowire n-channel junctionless and inversion mode MuGFETs has been compared. It has been observed that the subthreshold slopes are increased with the increase of the operation temperature in junctionless and inversio-mode transistors. The variation of a subthreshold slope with operation temperature is more significant in junctionless transistor than inversion-mode transistor. The temperature dependence on the variation of a subthreshold slope for different fin widths shows a similar behavior regardless of fin width. From the temperature dependence on the variation of a subthreshold slope for different substrate biases, it has been observed that the variation of a subthreshold slope is less significant when the substrate bias was applied. It is worth noting that one can achieve a subthreshold slope of below 41mV/dec at elevated temperature of 400K using the junctionless MuGFETs with a positive substrate bias.

Current-Voltage Characteristics with Substrate Bias in Nanowire Junctionless MuGFET (기판전압에 따른 나노와이어 Junctionless MuGFET의 전류-전압 특성)

  • Lee, Jae-Ki;Park, Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.785-792
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    • 2012
  • In this paper, a current-voltage characteristics of n-channel junctionless and inversion mode(IM) MuGFET, and p-channel junctionless and accumulation mode(AM) MuGFET has been measured and analyzed for the application in high speed and low power switching devices. From the variation of the threshold voltage and the saturation drain current with the substrate bias voltages, their variations in IM devices are larger than junctionless devices for n-channel devices, but their variations in junctioness devices are larger than AM devices for p-channel devices. The variations of transconductance with substrate biases are more significant in p-channel devices than n-channel devices. From the characteristics of subthreshold swing, it was observed that the S value is almost independent on the substrate biases in n-channel devices and p-channel junctionless devices but it is increased with the increase of the substrate biases in p-channel AM devices. For the application in high speed and low power switching devices using the substrate biases, IM device is better than junctionless devices for n-channel devices and junctionless device is better than AM devices for p-channel devices.

AC Electrical Coupling of Monolithic 3D Inverter Consisting of Junctionless FET (Junctionless FET로 구성된 적층형 3차원 인버터의 AC 특성에 대한 연구)

  • Kim, Kyung-won;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.529-530
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    • 2017
  • Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

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Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

  • Lee, Jae-Sung;Cho, Seong-Jae;Park, Byung-Gook;Harris, James S. Jr.;Kang, In-Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.230-239
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    • 2012
  • In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of $Y_{22}$-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

Device Design Guideline to Reduce the Threshold Voltage Variation with Fin Width in Junctionless MuGFETs (핀 폭에 따른 문턱전압 변화를 줄이기 위한 무접합 MuGFET 소자설계 가이드라인)

  • Lee, Seung-Min;Park, Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.135-141
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    • 2014
  • In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.