• Title, Summary, Keyword: H.264/AVC

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Implementation and Analysis of Performance Estimation Model of H.264/AVC Baseline Profile Decoder (H.264/AVC Baseline Profile Decoder의 성능 예측 모델의 구현과 분석)

  • Moon, Kyoung-Hwan;Song, Yong-Ho
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.44 no.3
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    • pp.108-123
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    • 2007
  • As H.264/AVC standard has proven to be a key technology of multimedia application, many researches to improve H.264/AVC standard are actively conducted. Those researches are conducted in various ways such as algorithm analysis and improvement or structure enhancement for reducing bottlenecks of performance. Even though targets and directions of those studies are not the same, performance of H.264/AVC standard is commonly analyzed in the early phase. In analysis phase, potential problems with H.264/AVC standard are identified and the most critical problem which has serious effects on performance is determined. Therefore, analysis phase is one of the important steps to decide overall directions and targets of the research. This research proposes a mathematical model which can be used in the early performance analysis phase to estimate performance in conducting research of improving the performance of H.264/AVC Baseline Profile decoder. The proposed model is designed by considering many variables of H.264/AVC decoder operation so that it is easy to predict its performance according to changes in each element.

An Implementation of a PCI Interface for H.264/AVC Encoder (H.264/AVC 인코더 용 PCI 인터페이스의 구현)

  • Park, Kyoung-Oh;Kim, Tae-Hyun;Hwang, Seung-Hoon;Hong, You-Pyo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.9A
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    • pp.868-873
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    • 2010
  • H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.

H.264/AVC to MPEG-2 Video Transcoding by using Motion Vector Clustering (움직임벡터 군집화를 이용한 H.264/AVC에서 MPEG-2로의 비디오 트랜스코딩)

  • Shin, Yoon-Jeong;Son, Nam-Rye;Nguyen, Dinh Toan;Lee, Guee-Sang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.5 no.1
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    • pp.23-30
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    • 2010
  • The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

UEP Turbo Encoder for H.264/AVC (H.264/AVC를 위한 UEP Turbo Encoder)

  • Kim, June;Kim, Youngseop;Park, In-Ho
    • Journal of the Semiconductor & Display Technology
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    • v.14 no.1
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    • pp.51-53
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    • 2015
  • H.264/AVC is international video coding standard, which shows improved code and efficiency than the existing video standards. H.264/AVC proposes data partitioning method that considerably to be an effective layering technique which separates important addressing data from the residual data. UEP(Unequal Error Protection) turbo code of H.264/AVC uses retransmission system to get the UEP effectively. However, Data partitioning system of H.264/AVC is inefficient method in turbo code of H.264/AVC. Based on this observation, we propose the new UEP turbo code algorithm that reconstructs input sequence of turbo code without retransmission system.

Implementation of IQ/IDCT in H.264/AVC Decoder Using GPGPU (GPGPU를 이용한 H.264/AVC 디코더)

  • Kim, Dong-Han;Lee, Kwang-Yeob
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.162-164
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    • 2010
  • H.264/AVC(Advanced Video Coding) is a standard for video compression. H.264/AVC provides good video quality at substantially lower bit rates than previous standards. In this papers, we propose the efficient architecture of H.264/AVC decoder using GPGPU. GPGPU can process many of operation in parallel. IQ/IDCT is possible that parallel processing in H.264/AVC decoding algorithm.

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A New Method for Thumbnail Extraction in H.264/AVC Bitstreams (H.264/AVC 비트스트림에서 썸네일 추출을 위한 새로운 방법)

  • Hong, Seung-Hwan;Kim, Ji-Eon;Chin, Young-Min;Kwon, Jae-Cheol;Oh, Seoung-Jun
    • Journal of Broadcast Engineering
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    • v.15 no.6
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    • pp.853-867
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    • 2010
  • Recently, thumbnail techniques are required to index a high-performance video at digital convergence-based multimedia service like IPTV and DMB. Therefore a thumbnail extraction method in H.264/AVC bitstreams has been proposed. However, thumbnail quality deterioration problem at converting the general equation of spatial domain to frequency domain which is generated by not considering about H.264/AVC transform and quantization processing and rounding-off operation in intra prediction. In this paper, we propose a new thumbnail extraction method in H.264/AVC bitstreams. The proposed scheme is based on H.264/AVC core-transform for a thumbnail extraction in frequency domain, and probability theory, intra rounding-off error compensation. Through the implementation and performance evaluation, the subjective quality difference between the output of our scheme and the output of reference decoder is negligible and better than the conventional method, and moreover PSNR gain by up to 8.66 dB.

An Efficient H.264/AVC Entropy Decoder Design (효율적인 H.264/AVC 엔트로피 복호기 설계)

  • Moon, Jeon-Hak;Lee, Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.102-107
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    • 2007
  • This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

Study on Image Distortions and Bit-rate Changes Induced by Watermark based-on $4{\times}4$ DCT of H.264/AVC (H.264/AVC의 $4{\times}4$ DCT기반 워터마크에 따른 영상왜곡과 비트율 변화에 대한 연구)

  • Kim, Sung-Min;Won, Chee-Sun
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.5
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    • pp.115-122
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    • 2005
  • There are some problems in directly applying the conventional MPEG bit-stream based watermarking schemes to the bit-stream of a new compression standard, H.264/AVC. In this paper we analyze the effects of the conventional DCT-based watermarking scheme to H.264/AVC, especially in terms of image distortions and bit-rate changes. It turns out that the intra-frame prediction md CAVLC of H.264/AVC with the watermarking worsen the image distortions and bit-rate changes. The experiment results show on average 28.17dB decrease in PSNR and 56.71% increase in bit-rate over all QPs.

Low-power IP Design and FPGA Implementation for H.264/AVC Encoder (H.264/AVC Encoder용 저전력 IP 설계 및 FPGA 구현)

  • Jang, Young-Beom;Choi, Dong-Kyu;Han, Jae-Woong;Kim, Do-Han;Kim, Bee-Chul;Park, Jin-Su;Han, Kyu-Hoon;Hur, Eun-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.5
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    • pp.43-51
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    • 2008
  • In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

Area-efficient Design of Intra Frame Decoder for H.264/AVC (H.264/AVC용 면적 효율적인 인트라 프레임 디코더 설계)

  • Jung, Duck-Young;Sonh, Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.11
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    • pp.2020-2025
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    • 2006
  • H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.