• Title, Summary, Keyword: Gate electrode

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A Study on Improvement of a-Si:H TFT Operating Speed

  • Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.42-44
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    • 2007
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

Electrical stabilities of half-Corbino thin-film transistors with different gate geometries

  • Jung, Hyun-Seung;Choi, Keun-Yeong;Lee, Ho-Jin
    • Journal of Information Display
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    • v.13 no.1
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    • pp.51-54
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    • 2012
  • In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.

Study of a Screen-Printed CNT Field Emitter with a Lateral-Gate Electrode (측면 게이트 전극을 이용한 스크린 프린트 되어진 탄소나노튜브 전계방출원의 연구)

  • Kim, Chang-Duk;Lee, Hyeong-Rag;Yang, Kiwon;Lee, Youngseok;Koo, Gyo Jun;Oh, Euidon;Song, Chang Yeon;Lee, Min Sub
    • New Physics: Sae Mulli
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    • v.67 no.3
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    • pp.352-356
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    • 2017
  • A triode electrode field emitter having a lateral-gate electrode was fabricated, and its characteristics were confirmed. Generally, a gate electrode with a lateral-gate electrode structure is formed in proximity to the cathode electrode. The cathode and the gate electrodes were formed by using a one-step process with carbon nanotubes (CNTs). The field emission of the diode electrode structure was measured before that of the triode electrode structure was. The turn-on voltage of the diode electrode structure was 240 V. The turn-on voltage of the triode electrode structure was 40 V higher than that of the diode electrode structure. However, all field emitted currents of the triode electrode structure were confirmed to flow to the anode electrode.

Fabrication of gate electrode for OTFT using screen-printing and wet-etching with nano-silver ink

  • Lee, Mi-Young;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.889-892
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    • 2009
  • We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

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$Ta/TaN_x$ Metal Gate Electrodes for Advanced CMOS Devices

  • Lee, S. J.;D. L. Kwong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.180-184
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    • 2002
  • In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

The Fabrication of a-Si:H TFT Improving Parasitic Capacitance of Source-Drain (소오스-드레인 기생용량을 개선한 박막트랜지스터 제조공정)

  • 허창우
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.821-825
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    • 2004
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ), a-Si:H(2000 ) and n+a-Si:H (500). We have deposited n+a-Si:H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

Optimization and Characterization of Gate Electrode Dependent Flicker Noise in Silicon Nanowire Transistors

  • Anandan, P.;Mohankumar, N.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1343-1348
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    • 2014
  • The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.

Numerical Analyses on Snapback-Free Shorted-Anode SOI LIGBT by using a Floating Electrode and an Auxiliary Gate (플로우팅 전극과 보조 게이트를 이용하여 스냅백을 없앤 애노드 단락 SOI LIGBT의 수치 해석)

  • O, Jae-Geun;Kim, Du-Yeong;Han, Min-Gu;Choe, Yeon-Ik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.2
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    • pp.73-77
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    • 2000
  • A dual-gate SOI SA-LIGBT (shorted-anode lateral insulated gate bipolar transistor) which eliminates the snapback effectively is proposed and verified by numerical simulation. The elimination of the snapback in I-V characteristics is obtained by initiating the hole injection at low anode voltage by employing a dual gate and a floating electrode in the proposed device. For the proposed device, the snapback phenomenon is completely eliminate, while snapback of conventional SA-LIGBT occurs at anode voltage of 11 V. Also, the drive signals of two gates have same polarity by employing the floating electrode, thereby requiring no additional power supply.

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Effect of gate electrode material on electrical characteristics of a-IGZO thin-film transistors (게이트 전극 물질이 a-IGZO 박막트랜지스터의 전기적 특성에 미치는 영향)

  • Oh, Hyungon;Cho, Kyoungah;Kim, Sangsig
    • Journal of IKEEE
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    • v.21 no.2
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    • pp.170-173
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    • 2017
  • In this study, we fabricate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with three different gate electrode materials of Al, Mo and Pt on plastic substrates and investigate their electrical characteristics. Compared to an a-IGZO TFT with Al gate electrode, the threshold voltage of an a-IGZO TFT with a Pt electrode decreases from -4.2 to -0.3 V. and the filed-effect mobility is improved from 15.8 to $22.1cm^2/V{\cdot}s$. The threshold voltage shift of the TFT is affected by the difference between the work function of the gate electrode and the Fermi energy of the channel layer. Moreover, the Pt gate electrode is considered to be the suitable material in terms of the electrical characteristics of the TFT. In addition, an description on an a-IGZO TFT with a Mo electrode will be given here.

Fabrication and Characterization of Organic Thin-Film Transistors by Using Polymer Gate Electrode (고분자 게이트 전극을 이용한 유기박막 트랜지스터의 제조 및 소자성능에 관한 연구)

  • Jang, Hyun-Seok;Song, Ki-Gook;Kim, Sung-Hyun
    • Polymer(Korea)
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    • v.35 no.4
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    • pp.370-374
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    • 2011
  • A conductive PANI solution was successfully fabricated by doping with camphorsulfonic acid and the polymerization of aniline and the confirmation of doping were characterized by FTIR spectroscopy. In organic thin film transistors, PANI gate electrodes were spin-coated on a PES substrate and their conductivity variations were monitored by a 4-probe method with different annealing temperatures. The surface properties of PANI thin films were investigated by an AFM and an optical microscope, OTFTs with PANI gate electrode had characteristics of carrier mobility as large as 0.15 $cm^2$/Vs and on/off ratio of $2.4{\times}10^6$, Au gate OTFTs with the same configuration were fabricated to investigate the effect of polymer gate electrode for the comparison of device performances. We could obtain the comparable performances of PANI devices to those of Au gate devices, resulting in an excellent alternative as an electrode in flexible OTFTs instead of an expensive Au electrode.