• Title, Summary, Keyword: FPGA

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Verification and Verification Method of Safety Class FPGA in Nuclear Power Plant (원자력발전소의 안전등급 FPGA 확인 및 검증 방법)

  • Lee, Dongil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.464-466
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    • 2019
  • Controllers used in nuclear power plants require high reliability. A controller including a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (referred to hereinafter as FPGA) has been applied to many Nuclear Power Plants (NPP) in the past, including the APR1400 (Advanced Power Reactor 1400), a Korean digital nuclear power plant. Initially, the FPGA was considered as a general IC (Integrated Circuit) and verified only by device verification and performance testing. In the 1990s, research on FPGA verification began, and until the FPGA became a chip, it was regarded as software and the software Verification and Validation (V&V) using IEEE 1012-2004 was implemented. Currently, IEC 62566, which is a European standard, has been applied for a lot of verification. This method has been evaluated as the most sensible method to date. This is because the method of verifying the characteristics of SoC (System on Chip), which has been a problem in the existing verification method, is sufficiently applied. However, IEC 62566 is a European standard that has not yet been adopted in the United States and maintains the application of IEEE 1012 for FPGA. IEEE 1012-2004 or IEC 62566 is a technical standard. In practice, various methods are applied to meet technical standards. In this paper, we describe the procedure and important points of verification method of Nuclear Safety Class FPGA applying SoC verification method.

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SoC Emulation in Multiple FPGA using Bus Splitter

  • Wooseung Yang;Lee, Seung-Jong;Ando Ki;Kyung, Chong-Min
    • Proceedings of the IEEK Conference
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    • pp.859-862
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    • 2003
  • This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

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A Study of Algorithm for Digital Technology (디지털 기술의 알고리즘에 관한 연구)

  • Youn, Choong-Mo;Kim, Jae-Jin
    • Journal of Digital Contents Society
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    • v.10 no.4
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    • pp.633-637
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    • 2009
  • In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

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Method of Multi-level Switching Function based on FPGA (FPGA를 이용한 멀티레벨 스위칭 함수 구현 방법)

  • Lee, Hwa-Chun;Song, Gee-Seok;Park, Sung-Jun;Lee, Min-Jung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.195-198
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    • 2008
  • Recently, with the growth of photovoltaic system, many researchers and companies have concerned about the multi-level inverter which has an efficiency of boosting voltage. This paper implements a multi-level switching function based on the FPGA. It is efficient to implement the switching function based on the FPGA as a program able logic device. In order to implementation the switching function, this paper synchronized with the microprocessor through the clock and synchronous signal from the microprocessor.

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Implementation of a Fast Current Controller using FPGA (FPGA를 이용한 고속 전류 제어기의 구현)

  • Jung, Eun-Soo;Lee, Hak-Jun;Sul, Seung-Ki
    • Proceedings of the KIPE Conference
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    • pp.223-225
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    • 2007
  • 본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP (Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시간을 감소시킬 수 있다. 이는 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반의 전류 제어기의 성능은 실험을 통해 검증되었다.

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Implementation of the Digital Current Control System for an Induction Motor Using FPGA (FPGA를 이용한 유도 전동기의 디지털 전류 제어 시스템 구현)

  • Yang, Oh
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.21-30
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    • 1998
  • In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

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Design of FPGA Adaptive Filter for ECG Signal Preprocessing (FPGA를 이용한 심전도 전처리용 적응필터 설계)

  • 한상돈;전대근;이경중;윤형로
    • Journal of Biomedical Engineering Research
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    • v.22 no.3
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    • pp.285-291
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    • 2001
  • In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

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REGO: REconfiGurable system emulatOr (레고 : 재구성 가능한 시스템 에뮬레이터)

  • Kim, Nam-Do;Yang, Se-Yang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.2
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    • pp.91-103
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    • 2002
  • For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

FPGA-DSP Based Implementation of Lane and Vehicle Detection (FPGA와 DSP를 이용한 실시간 차선 및 차량인식 시스템 구현)

  • Kim, Il-Ho;Kim, Gyeong-Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.12C
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    • pp.727-737
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    • 2011
  • This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.