• Title, Summary, Keyword: FPGA

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A multi-radio sink node designed for wireless SHM applications

  • Yuan, Shenfang;Wang, Zilong;Qiu, Lei;Wang, Yang;Liu, Menglong
    • Smart Structures and Systems
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    • v.11 no.3
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    • pp.261-282
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    • 2013
  • Structural health monitoring (SHM) is an application area of Wireless Sensor Networks (WSNs) which usually needs high data communication rate to transfer a large amount of monitoring data. Traditional sink node can only process data from one communication channel at the same time because of the single radio chip structure. The sink node constitutes a bottleneck for constructing a high data rate SHM application giving rise to a long data transfer time. Multi-channel communication has been proved to be an efficient method to improve the data throughput by enabling parallel transmissions among different frequency channels. This paper proposes an 8-radio integrated sink node design method based on Field Programmable Gate Array (FPGA) and the time synchronization mechanism for the multi-channel network based on the proposed sink node. Three experiments have been performed to evaluate the data transfer ability of the developed multi-radio sink node and the performance of the time synchronization mechanism. A high data throughput of 1020Kbps of the developed sink node has been proved by experiments using IEEE.805.15.4.

A Ripple Rejection Inherited RPWM for VSI Working with Fluctuating DC Link Voltage

  • Jarin, T.;Subburaj, P.;Bright, Shibu J V
    • Journal of Electrical Engineering and Technology
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    • v.10 no.5
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    • pp.2018-2030
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    • 2015
  • A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

A Response Time of the Nuclear Emergency Preparedness Robot based on the Gamma Ray Dose-Rate Constraints (감마선 선량율 제한조건에 따른 원자력 비상대응로봇의 대응시간)

  • Cho, JaiWan;Choi, Young Soo;Kim, TaeWon;Jeong, KyungMin
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.807-810
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    • 2014
  • 로봇 시스템의 제어 및 이를 이용한 환경 인식에는 많은 전자 광학 소자들이 사용되고 있다. 로봇 제어회로에 사용되고 있는 Si CMOS 공정의 CPU, ASIC, FPGA 소자는 고 선량의 감마선에 취약하다. 환경정보 수집용으로 로봇에 탑재되는 CMOS/CCD 카메라의 관측영상에는 고선량 감마선으로 인한 speckle (백색잡음, white noise) 들이 나타나며, 이들이 카메라의 관측성능을 저하시킨다. 후쿠시마 원자력발전소 사고와 같이 원자력시설에서 제어불능의 심각한 사고가 발생되면 고선량 감마선이 방출된다. 이러한 고선량 감마선방출은 사람에 의한 사고수습을 불가능하게 하며, 사고 수습을 위해서는 로봇의 활용이 불가피하다. 그러나, 방출되는 고선량 감마선의 세기(선량율)가 지나치게 높을 경우, 로봇 전자회로가 장애를 일으키기 때문에 로봇의 적절한 임무수행이 가능한 감마선 세기에 대한 고려가 필요하다. 본 논문에서는 고선량 감마선 환경하에서의 로봇 탑재 CCD/CMOS 카메라의 관측 성능을 고려하여 100 Gy/h 를 감마선 선량율 제한조건으로 설정한다. 그리고, 재 가동 승인심사를 받기 위해 일본의 원전 운영자들이 제시한 PWR (가압경수로) 원전의 중대사고 대책 적합성 평가문서에 나타난 노심용융개시 시점의 원자로 격납건물내 감마선 선량율 추이 계산결과를 활용하여 로봇의 대응시간을 계산하였다. 문서 (PDF) 에 표현된 감마선 선량율 추이 그래프를 영상 판독하여, 격납건물내 감마선 선량율이 100 Gy/h 제한조건에 도달하는 시간을 계산하였다. 이를 로봇의 대응시간으로 설정한다.

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ATM Cell Encipherment Method using Rijndael Algorithm in Physical Layer (Rijndael 알고리즘을 이용한 물리 계층 ATM 셀 보안 기법)

  • Im Sung-Yeal;Chung Ki-Dong
    • The KIPS Transactions:PartC
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    • v.13C no.1
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    • pp.83-94
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    • 2006
  • This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

Development of a Small Animal Positron Emission Tomography Using Dual-layer Phoswich Detector and Position Sensitive Photomultiplier Tube: Preliminary Results (두층 섬광결정과 위치민감형광전자증배관을 이용한 소동물 양전자방출단층촬영기 개발: 기초실험 결과)

  • Jeong, Myung-Hwan;Choi, Yong;Chung, Yong-Hyun;Song, Tae-Yong;Jung, Jin-Ho;Hong, Key-Jo;Min, Byung-Jun;Choe, Yearn-Seong;Lee, Kyung-Han;Kim, Byung-Tae
    • The Korean Journal of Nuclear Medicine
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    • v.38 no.5
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    • pp.338-343
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    • 2004
  • Purpose: The purpose of this study was to develop a small animal PET using dual layer phoswich detector to minimize parallax error that degrades spatial resolution at the outer part of field-of-view (FOV). Materials and Methods: A simulation tool GATE (Geant4 Application for Tomographic Emission) was used to derive optimal parameters of small PET, and PET was developed employing the parameters. Lutetium Oxyorthosilicate (LSO) and Lutetium-Yttrium Aluminate-Perovskite(LuYAP) was used to construct dual layer phoswitch crystal. $8{\times}8$ arrays of LSO and LuYAP pixels, $2mm{\times}2mm{\times}8mm$ in size, were coupled to a 64-channel position sensitive photomultiplier tube. The system consisted of 16 detector modules arranged to one ring configuration (ring inner diameter 10 cm, FOV of 8 cm). The data from phoswich detector modules were fed into an ADC board in the data acquisition and preprocessing PC via sockets, decoder block, FPGA board, and bus board. These were linked to the master PC that stored the events data on hard disk. Results: In a preliminary test of the system, reconstructed images were obtained by using a pair of detectors and sensitivity and spatial resolution were measured. Spatial resolution was 2.3 mm FWHM and sensitivity was 10.9 $cps/{\mu}Ci$ at the center of FOV. Conclusion: The radioactivity distribution patterns were accurately represented in sinograms and images obtained by PET with a pair of detectors. These preliminary results indicate that it is promising to develop a high performance small animal PET.

Implementation of a Grant Processor for Upstream Cell Transmission at the ONU in the ATM-PON (ATM-PON의 ONU에서 상향 셀 전송을 위한 승인처리기의 구현)

  • 우만식;정해;유건일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.5C
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    • pp.454-464
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    • 2002
  • In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

Design of Video Encoder activating with variable clocks of CCDs for CCTV applications (CCTV용 CCD를 위한 가변 clock으로 동작되는 비디오 인코더의 설계)

  • Kim, Joo-Hyun;Ha, Joo-Young;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.1
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    • pp.80-87
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    • 2006
  • SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

Implementation of High-Throughput SHA-1 Hash Algorithm using Multiple Unfolding Technique (다중 언폴딩 기법을 이용한 SHA-1 해쉬 알고리즘 고속 구현)

  • Lee, Eun-Hee;Lee, Je-Hoon;Jang, Young-Jo;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.41-49
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    • 2010
  • This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

Performance of Energy Efficient Optical Ethernet Systems with a Dynamic Lane Control Scheme (동적 레인 제어방식을 적용한 에너지 절감형 광 이더넷 시스템의 성능분석)

  • Seo, Insoo;Yang, Choong-Reol;Yoon, Chongho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.11
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    • pp.24-35
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    • 2012
  • In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

Design and Implementation of a Hardware-based Transmission/Reception Accelerator for a Hybrid TCP/IP Offload Engine (하이브리드 TCP/IP Offload Engine을 위한 하드웨어 기반 송수신 가속기의 설계 및 구현)

  • Jang, Han-Kook;Chung, Sang-Hwa;Yoo, Dae-Hyun
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.9
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    • pp.459-466
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    • 2007
  • TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.