• Title, Summary, Keyword: ESD

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System Level ESD Analysis - A Comprehensive Review II on ESD Coupling Analysis Techniques

  • Yousaf, Jawad;Lee, Hosang;Nah, Wansoo
    • Journal of Electrical Engineering and Technology
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    • v.13 no.5
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    • pp.2033-2044
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    • 2018
  • This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

The Design of SCR-based Whole-Chip ESD Protection with Dual-Direction and High Holding Voltage (양 방향성과 높은 홀딩전압을 갖는 사이리스터 기반 Whole-Chip ESD 보호회로)

  • Song, Bo-Bae;Han, Jung-Woo;Nam, Jong-Ho;Choi, Yong-Nam;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.378-384
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    • 2013
  • We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

HBM ESD Tester for On-wafer Test using Flyback Method (Flyback방식을 이용한 on-wafer용 HBM ESD 테스터 구현)

  • 박창근;염기수
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.469-472
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    • 2002
  • We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flyback method, we can isolate the low voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STll-883D). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

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Design of ESD Protection Circuits for High-Frequency Integrated Circuits (고주파 집적회로를 위한 ESD 보호회로 설계)

  • Kim, Seok;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.36-46
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    • 2010
  • In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

HBM ESD Tester for On-wafer Test using Flyback Method (Flyback 방식을 이용한 on-wafer용 HBM ESD 테스터 구현)

  • 박창근;염기수
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.7
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    • pp.1079-1083
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    • 2002
  • We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMSIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flvback method, we can isolate the 1ow voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STD). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

Stress mode proposal for an efficient ESD test (효율적인 ESD(ElectroStatic Discharge) test를 위한 Stress mode 제안)

  • Gang, Ji-Ung;Chang, Seog-Weon;Kwack, Kae-Dal
    • Proceedings of the KSME Conference
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    • pp.1289-1294
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    • 2008
  • Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.

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Analyzing the Education for Sustainable Development (ESD) Club Programs Connecting with the Local Communities' Organizations in Elementary and Middle Schools (지역사회기관과의 연계 활동을 목적으로 한 초·중학교 지속가능발전교육 동아리 프로그램 분석)

  • SON, Yeon-A
    • Journal of Fisheries and Marine Sciences Education
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    • v.27 no.6
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    • pp.1797-1811
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    • 2015
  • This study is to analyze the local community-connected Education for Sustainable Development (ESD) programs that 17 clubs' students and teachers developed and implemented for their ESD club activities in elementary and middle schools. For this study, ESD elements in the programs are analyzed and the way of connection between the local communities' organizations and the ESD clubs is inquired. The process of ESD club activities is also analyzed and the change of students after the local community-connected ESD club activities is examined. Finally, the way of dissemination to local communities after ESD club activities is inquired. This study is to contribute to the practice of the local community-connected ESD in a way that develops core competencies in elementary and middle school students that will allow them to build a sustainable future in local communities.

A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted (Parallel PNP 및 N+ drift가 삽입된 높은 홀딩전압특성을 갖는 ESD보호회로에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.24 no.3
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    • pp.890-894
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    • 2020
  • In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

A Study on LVTSCR-Based N-Stack ESD Protection Device with Improved Electrical Characteristics (향상된 전기적 특성을 지닌 LVTSCR 기반의 N-Stack ESD 보호소자에 관한 연구)

  • Jin, Seung-Hoo;Woo, Je-Wook;Joung, Jang-Han;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.168-173
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    • 2021
  • In this paper, we propose a new structure of ESD protection device that achieves improved electrical characteristics through structural change of LVTSCR, which is a general ESD protection device. In addition, it applies N-Stack technology for optimized design in the ESD Design Window according to the required voltage application. The N-Well area additionally inserted in the existing LVTSCR structure provides an additional ESD discharge path by electrically connecting to the anode, which improves on-resistance and temperature characteristics. In addition, the short trigger path has a lower trigger voltage than the existing LVTSCR, so it has excellent snapback characteristics. In addition, Synopsys' T-CAD Simulator was used to verify the electrical characteristics of the proposed ESD protection device.

System Level ESD Analysis - A Comprehensive Review I on ESD Generator Modeling

  • Yousaf, Jawad;Lee, Hosang;Nah, Wansoo
    • Journal of Electrical Engineering and Technology
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    • v.13 no.5
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    • pp.2017-2032
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    • 2018
  • This study presents, for the first time, state-of-the art review of the various techniques for the modeling of the electrostatic discharge (ESD) generators for the ESD analysis and testing. After a brief overview of the ESD generator, the study provides an in-depth review of ESD generator modeling (analytical, circuit and numerical modeling) techniques for the contact discharge mode. The proposed techniques for each modeling approach are compared to illustrates their differences and limitations.