• Title, Summary, Keyword: Capacitance-voltage

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Capacitive Touch Switch Regardless of Operating Frequency Using a Switched-Capacitor (스위치드 커패시터를 이용한 동작 주파수에 무관한 정전용량 터치스위치)

  • Lee, Mu-Jin;Seong, Kwang-Su
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.6
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    • pp.88-94
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    • 2013
  • This paper proposes a capacitive touch switch using a switched-capacitor. The proposed method charges capacitance for measurement using the switched-capacitor until the voltage across the capacitance reaches a threshold voltage. As the proposed method uses the number of times being charged to measure the capacitance, the method has no relation with the operating frequency of the switched-capacitor. This paper also shows the quantization resolution of the proposed method is related to the capacitance in the switched-capacitor and the threshold voltage, i.e., the resolution is improved when the capacitance in the switched-capacitor is decreased and the threshold voltage is increased. Simulation result shows the method gives 31fF quantization resolution when the capacitance in the switched-capacitor is 50fF and threshold voltage is 80% of the supply voltage.

Response Characteristics for Low Voltage Liquid Crystal Display Employing a Constant Charge Model

  • Kim, Mi-Soon;Huh, Su-Jung;Suh, Duck-Jong;Ahn, Yi-Joon;Lee, Kyung-Jin;Ahn, Seon-Hong;Kim, Kyeong-Hyeon;Kim, Sang-Soo
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.228-230
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    • 2008
  • The response time characteristic of low voltage liquid crystals (LCs) is investigated and a new simulator for low voltage LCs is proposed. In order to enable low voltage operation, it is important to minimize Vth of LCs and variation of pixel voltage caused by dynamic capacitance operation of LC Display. Because dynamic capacitance variation is much larger for low voltage LC operation compared to that of conventional LC material, it is necessary to make a better model for dynamic capacitance operation. A proposed minimizing Vth of LCs and variation of pixel voltage study results through a new constant charge model improve response characteristics for low voltage LCs operation.

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Large Signal Determination of Non-Linear Output Capacitance of Gallium-Nitride Field Effect Transistors from Switch-Off Voltage Transients - A Numerical Method

  • Pentz, David;Joannou, Andrea
    • Journal of Power Electronics
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    • v.18 no.6
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    • pp.1912-1919
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    • 2018
  • The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

Capacitance Estimation Method of DC-Link Capacitors for BLDC Motor Drive Systems

  • Moon, Jong-Joo;Kim, Yong-Hyu;Park, June-Ho;Kim, Jang-Mok
    • Journal of Electrical Engineering and Technology
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    • v.11 no.3
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    • pp.653-661
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    • 2016
  • This paper proposes a capacitance estimation method of the dc-link capacitor for brushless DC motor (BLDCM) drive systems. In order to estimate the dc-link capacitance, the BLDCM is operated in quadrant-II or -IV among four-quadrant operation. Quadrant-II and -IV are called reverse braking and forward braking, respectively. During the braking operation of the BLDCM, the capacitor is charged by the phase current and then the voltage is increased during the braking operation time. The capacitor current and voltage can be obtained by using the phase current sensor of BLDCM and the dc-link voltage sensor. The capacitance and be easily obtained by the voltage equation of the capacitor. The proposed method guarantees the reliable and simple calculation of the dc-link capacitance without additional hardware system except several the sensors already installed for the motor control system. The effectiveness of the proposed method is verified through both the simulation and experimental results.

Accurate RF C-V Method to Extract Effective Channel Length and Parasitic Capacitance of Deep-Submicron LDD MOSFETs

  • Lee, Sangjun;Lee, Seonghearn
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.653-657
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    • 2015
  • A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

A Study of the Relationship Analysis of Power Conversion and Changed Capacitance in the Depletion Region of Silicon Solar Cell

  • Kim, Do-Kyeong;Oh, Yeong-Jun;Kim, Sang-Hyun;Hong, Kyeong-Jin;Jung, Haeng-Yeon;Kim, Hoy-Jin;Jeon, Myeong-Seok
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.4
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    • pp.177-181
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    • 2013
  • In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.

Measurement of Voltage Transfer Curve in AC PDP (AC-PDP특성평가를 위한 전압전달곡선 계측에 관한 연구)

  • 손진부;이성현;김동현;김영대;조정수;박정후
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.395-398
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    • 1999
  • In ac PDP(plasma Display Panel), the discharge characteristics is very important to display clear images. In this paper, we have studied the measurement of voltage transfer curves which show the discharge characteristics in AC PDP. The change of the effective wall capacitance during a discharge is also studied. These depend on lateral spreading of charge distribution and the strength of the discharge. As a parameter of the frequency, we observed the effects of the frequency in voltage transfer curves and in effective wall capacitance changes. As frequency increases, minimum sustain voltage and firing voltage decrease. In upper region of gap voltage the chance of the effective wall capacitance is independent of frequency.

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Accurate Extraction of the Effective Channel Length of MOSFET Using Capacitance Voltage Method (Capacitance - Voltage 방법을 이용한 MOSFET의 유효 채널 길이 추출)

  • 김용구;지희환;한인식;박성형;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.1-6
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    • 2004
  • For MOSFET devices with nanometer range gate length, accurate extraction of effective gate length is highly important because transistor characteristics become very sensitive to effective channel length. In this paper, we propose a new approach to extract the effective channel length of nanometer range MOSFET by Capacitance Voltage(C-V) method. The effective channel length is extracted using gate to source/drain capacitance( $C_{gsd}$). It is shown that 1/$\beta$ method, Terada method and other C-V method are inadequate to extract the accurate effective channel length. Therefore, the proposed method is highly effective for extraction of effective channel length of 100nm CMOSFETs.s.

Design Guidelines for a Capacitive Wireless Power Transfer System with Input/Output Matching Transformers

  • Choi, Sung-Jin
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1656-1663
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    • 2016
  • A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.