• Title, Summary, Keyword: CMOS

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Primitive IPs Design Based on a Memristor-CMOS Circuit Technology (멤리스터-CMOS 회로구조 기반의 프리미티브 IP 설계)

  • Han, Ca-Ram;Lee, Sang-Jin;Eshraghian, Kamran;Cho, Kyoungrok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.4
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    • pp.65-72
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    • 2013
  • This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

Development of Si(110) CMOS process for monolithic integration with GaN power semiconductor (질화갈륨 전력반도체와 Si CMOS 소자의 단일기판 집적화를 위한 Si(110) CMOS 공정개발)

  • Kim, Hyung-tak
    • Journal of IKEEE
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    • v.23 no.1
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    • pp.326-329
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    • 2019
  • Gallium nitride(GaN) has been a superior candidate for the next generation power electronics. As GaN-on-Si substrate technology is mature, there has been new demand for monolithic integration of GaN technology with Si CMOS devices. In this work, (110)Si CMOS process was developed and the fabricated devices were evaluated in order to confirm the feasibility of utilizing domestic foundry facility for monolithic integration of Si CMOS and GaN power devices.

A Study on the Characteristics of BiCMOS and CMOS Inverters (BiCMOS 및 CMOS로 구현된 Inverter에 대한 특성비교)

  • 정종척;이계훈;우영신;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.93-96
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    • 1993
  • BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

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Design of MYNAMIC CMOS ARRAY LOGIC (DYNAMIC CMOS ARRAY LOGIC의 설계)

  • 한석붕;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.10
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    • pp.1606-1616
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    • 1989
  • In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

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The Study of Analog CMOS Process Technology (아날로그 CMOS 공정기술 연구)

  • No, Tae-Mun;Lee, Dae-U;Kim, Gwang-Su;Gang, Jin-Yeong
    • Electronics and Telecommunications Trends
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    • v.10 no.1
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    • pp.1-17
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    • 1995
  • 본 연구에서는 아날로그 CMOS IC 제조를 위한 CMOS 소자기술 및 수동소자 기술인, 다결정실리콘 저항과 다결정실리콘(I)/산화막/다결정실리콘(II) 구조를 가진 커패시터의 공정기술을 개발하였다. 아날로그 CMOS 공정기술은 디지털 CMOS 공정에서 다결정실리콘 저항과 커패시터 공정이 추가됨으로씨 발생할 수 있는 CMOS 소자특성의 변화를 최소화하는 데 중점을 두어 개발하였다. 최종적으로 개발된 $1.2\mum$ 아날로그 CMOS 공정을 이용하여 10 비트 ADC 및 DACIC를 제작한 후 정상적인 동작을 확인함으로써, $1.2\mum$ 아날로그 CMOS 공정에 의한 아날로그 IC 제작의 응용 가능성을 검증하였다. 개발된 $1.2\mum$ 아날로그 CMOS 공정은 향후 $0.8\mum$ 아날로그 CMOS IC 개발에 크게 기여할 것으로 기대된다.

A Design of Full Flash 8-Bit CMOS A/D Converter (Full Flash 8-Bit CMOS A/D 변환기 설계)

  • Choi, Young-Gyu;Yi, Cheon-Hee
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.11
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    • pp.126-134
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    • 1990
  • In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

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A Study On Radiation Detection Using CMOS Image Sensor (CMOS 이미지 센서를 사용한 방사선 측정에 관한 연구)

  • Lee, Joo-Hyun;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.19 no.2
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    • pp.193-200
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    • 2015
  • In this paper, we propose the radiation measuring algorithm and the device composition using CMOS image sensor. The radiation measuring algorithm using CMOS image sensor is based on the radiation particle distinguishing algorithm projected to the CMOS image sensor and accumulated and average number of pixels of the radiation particles projected to dozens of images per second with CMOS image sensor. The radiation particle distinguishing algorithm projected to the CMOS image sensor measures the radiation particle images by dividing them into R, G and B and adjusting the threshold value that distinguishes light intensity and background from the particle of each image. The radiation measuring algorithm measures radiation with accumulated and average number of radiation particles projected to dozens of images per second with CMOS image sensor according to the preset cycle. The hardware devices to verify the suggested algorithm consists of CMOS image sensor and image signal processor part, control part, power circuit part and display part. The test result of radiation measurement using the suggested CMOS image sensor is as follows. First, using the low-cost CMOS image sensor to measure radiation particles generated similar characteristics to that from measurement with expensive GM Tube. Second, using the low-cost CMOS image sensor to measure radiation presented largely similar characteristics to the linear characteristics of expensive GM Tube.

A Study on the Computer Modelling with Process Parameters for the Optimization of BiCMOS Device (Process Parameter의 Modelling에 의한 BiCMOS 소자 설계의 최적화 방안에 관한 연구)

  • Kang, Ey-Goo;Kim, Tae-Ik;Woo, Young-Shin;Lee, Kye-Hun;Sung, Man-Young;Lee, Cheol-Jin
    • Proceedings of the KIEE Conference
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    • pp.1460-1462
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    • 1994
  • BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

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The Open Loop Multiple Split Ring Resonator Based Voltage Controlled Oscillator in 0.13 um CMOS (개방 루프 다중 분할 링 공진기를 이용한 0.13 um 전압 제어 발진기 설계)

  • Kim, Hyoung-Jun;Choi, Jae-Won;Seo, Chul-Hun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.2
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    • pp.202-207
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    • 2010
  • In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

Disign Technique and Testability Analysis of High Speed Full-Swing BiCMOS Circuits (테스트가 용이한 고속 풀 스윙 BiCMOS회로의 설계방식과 테스트 용이도 분석)

  • Lee, Jae Min;Jung, Kwang Sun
    • Journal of the Korean Society of Industry Convergence
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    • v.4 no.2
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    • pp.199-205
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    • 2001
  • With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.

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